01-30-2019 09:01 AM
I have a module that does 25 x 35 multiplications (multipliers are inferred, bot instantiated directly). I get the following warning during place_design.
[DRC REQP-1723] DSP_Abus_sign_bit_restriction: Servo0/Diff/DyNew0: When using the PreAdder and USE_DPORT is TRUE, the A operand should be restricted to 24 bit two's complement (and sign extended) to avoid over/underflow in the pre-add stage.
How should I approach resolving this warning? Could it be leading to bugs when the code is running on the FPGA?
02-06-2019 04:06 PM
your last question... could it lead to bugs? ... A couple of things to consider...
1) Do you have control the range of the input data? (e.g. will it ever get in the range that could cause an overflow?)
2) Do you have a methodolgy you want to use when/if it encounters an overflow? (e.g. do you have the luxury to ignore that case?)
Hope that helps
If so, please mark as solution accepted to close the issue. Kudos also welcomed. :-)
02-06-2019 04:15 PM
I'm not clear on whether you're inferring DSP48 or instantiating them - but in either case Vivado should generate a netlist that matches the RTL description. If for some reasons the tool can't generate it efficiently with the underlying logic - then the warning is justified. It should be just an efficiency/optimization warning.
If the tools is building something that doens't match your RTL description, then that's a severe tool bug - regardless of whether or not a warning is generated.
I don't know which of the above types this message you're seeing is implying - I'm hoping the former. I'd be interested in what Xilinx says regarding the message.
Not offering much help, but just concern of my own...