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Visitor dnhkng
Visitor
3,235 Views
Registered: ‎05-05-2017

Need help connecting pin constraints XDC file ports to Block Diagram.

Hi Xilinx,

 

I have a few dev boards (CMOD A7, Zedboards, Arty Z7 etc). They all come with constraints file for the hardware pins, i.e. LED's, GPIO ports, XADC adc p/n pairs, etc, often bunched in ports like {led_o[*]}. The file sets the voltage, the physical pin, and the port name (single pin or an array, i.e. pin or {pins[*]} ).

 

When I make a new Block Diagram and I add a AXI-GPIO block, how can I link the ports defined in the constraints file to the AXI-GPIO IP block output or input port?

 

Similarly,  when I add an XADC IP block and I then add some channels and make the ports external, (eg Vaux0 + Vaux1 + Vaux9), how do I make sure they connect to the ports defined the the constraints file?

 

I have seen that Board File ports can be dropped into Block Diagrams, but I can't see how to do the same with XDC file pin constraints.

 

Thanks,

David

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3 Replies
Voyager
Voyager
3,212 Views
Registered: ‎03-28-2016

Re: Need help connecting pin constraints XDC file ports to Block Diagram.

In most cases, you will want to create a new constraints file for each design that you create. 

 

The constraints files that are associated with a development board are either a master constrains file or a constraints file that is tied to a specific reference design.  Use them as a reference to create you new constraints files.

 

You can build a new constraints file a couple of different ways:

  1. Vivado GUI
    1. In Vivado, synthesize your design.
    2. When synthesis completes, open the Synthesized Design
    3. In the top right corner of Vivado, change the "Default Layout" view to the "I/O Planning" view.  This will open an I/O Ports tab at the bottom of the window.  This shows how all of the pins are defined in your design.
    4. In the I/O Ports tab, set the pin location for each pin using the "Package Pin" column.  Set the I/O Standard for each pin using the "I/O Std" column.  You may need to expand the "Name" column to see all of the pins.
    5. Save the new XDC file.  It should automatically be added to your projecct.
  2. Manual Text File
    1. Create a new XDC file or make a copy of an existing XDC file
    2. Manually enter the Pin locations and I/O Standards for all of the I/O in your design.  Make sure the pin names match the names of the I/O in your design.
    3. Save the new XDC file.
    4. In Vivado, add the new XCD file to the Design Sources in your project.

Hope this helps.

 

Ted Booth - Tech. Lead FPGA Design Engineer
www.designlinxhs.com
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Visitor dnhkng
Visitor
3,205 Views
Registered: ‎05-05-2017

Re: Need help connecting pin constraints XDC file ports to Block Diagram.

Hi Ted,

 

I have been using option 2, as I use the XDC master to quickly copy-and-paste in the pins I need to use in my design. 

 

But I still don't see a way to get the ports defined in my XDC constraints file to appear on my Block Diagram.

 

What I want to be able to do is this:

  1. Define some ports in a constraints file (Voltage, Package Pin/s, Port Name)
  2. add to the Block Diagram the IP blocks i need for my design (e.g. ZYNQ7 PS, XADC Wizard, AXI-GPIO etc.)
  3. add to the Block Diagram the ports I created in step one
  4. wire everything together!

Is this possible? It seems like the logical way to do things!

 

Thanks,

David

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Voyager
Voyager
3,153 Views
Registered: ‎03-28-2016

Re: Need help connecting pin constraints XDC file ports to Block Diagram.

Yes, you can certainly do what you are describing.  Although, I typically do it in a slightly different order.  I typically do the XDC file last.

 

When you add the ports to your block diagram.  Make sure that the name of the port exactly matches the name used in the XDC file.

 

Before you can compile your block diagram, it has to have an HDL wrapper around it which you typically have Vivado generate for you.  Assuming that this wrapper file is your "Top-Level Module", open it and make sure that the IO ports listed there match the port names in your XDC file.  Also make sure that your XDC file has been added as a source to your project. 

 

Ted Booth - Tech. Lead FPGA Design Engineer
www.designlinxhs.com
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