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townsend
Observer
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Registered: ‎02-08-2019

Need help in Changing Clock

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I have a Xilinx Nexys A7 which uses the Artix-7 100T FPGA. The clock I am using for my solution is 100MHz which I guess is the default. Is it possible to do something (clock multiplier?) to crank it up to 200Mhz to see if my solution can still keep up to that speed? I'v looked at some technical information about clock tiles and so on but can't sort out what to do. Can someone please give me a list of simple instructions to follow? The only thing I have in my solution that appears to be related is in the constraints file where I see this line:

## Clock signal
set_property -dict {PACKAGE_PIN E3 IOSTANDARD LVCMOS33} [get_ports clk]
create_clock -period 10.000 -name sys_clk_pin -waveform {0.000 5.000} -add [get_ports clk]

 

I've naively tried to just change the above to 

create_clock -period50.000 -name sys_clk_pin -waveform {0.000 2.500} -add [get_ports clk]

 

But this changed nothing.

-gt-

 

 

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yashp
Moderator
Moderator
758 Views
Registered: ‎01-16-2013

Hi,

I have moved this post from ML Suite to Design entry. Always post your query in associated board to get faster response as most of the experts follow their community board actively.

Regarding your query: You have just changed the constraint of clock defination this won't change anything in hardware. If you wanted to change the hardware for 100MHz to 200MHz clock you need to instantiate the MMCM/PLL (clocking wizard IP) this clock tile helps to synthesize the clock. 

You can provide your input as 100MHz and as per configuration the generated clock will be with new defination as well as the same will be present in hardware.

NOTE: As you have mentioned in your one comment that you will write verilog code (I guess you are talking about some logic to synthesize the clock) but fabric generated clocks are not recommended as it has high skew issues.

Thanks,
Yash

 

 

 

 

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4 Replies
drjohnsmith
Teacher
Teacher
806 Views
Registered: ‎07-09-2009

the clock you are refering to I htink is the clock into the fpga.

   this is fixed by the board, have you changed the oscilator on the board ?

 

Using the MMCM of the FPGA you can and probably are chaning that 100 Mhz into another clock ,

      the MMCM can go up to a few hundred Mhz,

        but you need to change the code, not the constraints , you would stil put 100 MHz into the fpga.

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
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townsend
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Registered: ‎02-08-2019

Thanks for the reply. What you said is what I assumed I would have to do i.e. it remains clocked from the onboard 100MHz oscillator, but I do "something" in my verilog code to produce a new clock from this 100MHz signal, but that's precisely where I need help. What exactly do I do to produce a new clock signal to clock my solution with using this "MMCM" thing you mentioned? I can't find any simple example code where this is implemented. Is it something I code up in verilog, or something I have to select in Vivado by pointing and clicking using the GUI to produce the desired new clock signal? I'm looking for a simple list of instructions to follow to accomplish this. Thanks!

-gt-

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drjohnsmith
Teacher
Teacher
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Registered: ‎07-09-2009
easiest way would be to run the clock wizard / ip in vivado.
configure this to the requirements you need, and just instantiate it in your code.
<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
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yashp
Moderator
Moderator
759 Views
Registered: ‎01-16-2013

Hi,

I have moved this post from ML Suite to Design entry. Always post your query in associated board to get faster response as most of the experts follow their community board actively.

Regarding your query: You have just changed the constraint of clock defination this won't change anything in hardware. If you wanted to change the hardware for 100MHz to 200MHz clock you need to instantiate the MMCM/PLL (clocking wizard IP) this clock tile helps to synthesize the clock. 

You can provide your input as 100MHz and as per configuration the generated clock will be with new defination as well as the same will be present in hardware.

NOTE: As you have mentioned in your one comment that you will write verilog code (I guess you are talking about some logic to synthesize the clock) but fabric generated clocks are not recommended as it has high skew issues.

Thanks,
Yash

 

 

 

 

View solution in original post