11-07-2018 02:17 PM
This is with Vivado 2018.2.
I have ILA cores instantiated in multiple locations in my design. Randomly, the nets are renamed during synth/imp process so they display incorrectly when debugging with the hardware manager. I've noticed this happens typically when debugging multiple nets which are all connected continuously. Obviously a solution is to only debug one of the nets, however I have this setup to simplify the debugging and analysis process for non-FPGA team members, who only want to have to look at the debugger for analysis and not Verilog code.
An example code screenshot and waveform result is posted. Notice how some nets in question (state_next, i_dvalid, o_dvalid) are renamed to some variation of "state_next_x", and "o_dvalid" is renamed to "i_dvalid_1", which of course is extremely confusing for anyone viewing the waveform. The values are all correct, it would just be nice if the tool wouldn't rename my signals. I don't want to have to go into the .ltx file and do it every time manually.
11-07-2018 05:16 PM
Does it help if you add MARK_DEBUG attribute to the probe signals?
(* MARK_DEBUG = "TRUE" *) wire o_valid;
This is supposed to prevent optimization that might have otherwise occurred to the signal.
11-08-2018 11:50 AM
I'll try that, but would prefer to not have to leave debug markers all over the code.
I'd think ILA cores should have constraints for this sort of thing.