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simonh_bwt
Adventurer
Adventurer
3,365 Views
Registered: ‎02-08-2016

OOC Synthesis - Design run wrongly reports name of constraint set

Hi,

 

I am using OOC synthesis flow.

 

I have run synthesis successfully. However the Design Runs panel wrongly reports the constraint set I use. I am only using one constraint set "OOC_constraints", yet the Constraints column of the Design runs panel is reporting a constraints set of "bh2_pcie_clean_wrap" which is the name of the sources set.

 

The Synthesis Run Properties Window - also shown also miss-reports this.

 

Is my observation correct? If so has this feature been fixed in Vivado 2017.1

 

Thanks Simon

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simonh_bwt
Adventurer
Adventurer
3,363 Views
Registered: ‎02-08-2016

Picture attached ... missing from above

ooc_1.png
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florentw
Moderator
Moderator
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Registered: ‎11-09-2015

Hi @simonh_bwt,

 

I don't think this is an issue. This is more a different way to synthesis in out-of-context mode.

 

The target constaint folder in Vivado is more for the general synthesis than for the OOC.

 

You may want to try to follow the "Setting a Bottom-Up Out-of-Context Flow" from the UG901 p23.

 

Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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simonh_bwt
Adventurer
Adventurer
3,346 Views
Registered: ‎02-08-2016

Hi FlorentW,

 

Thanks for your reply. In fact I am following the documentation pages 23-25 of UG901, as I wish to put in place a bottom-up OO flow.

 

My point is that the user interface is not identifying the correct set of constraints for the OOC synthesis. I have only one set of constraints that I apply to my OOC synth module, if there were several constraints sets how would I know which one I had used? Furthermore if the output from the OOC synthesis is in the .dcp format, then I am unable to verify later which constraint set I had used.

 

Regards

 

Simon

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