05-19-2017 05:45 AM
I am using OOC synthesis flow.
I have run synthesis successfully. However the Design Runs panel wrongly reports the constraint set I use. I am only using one constraint set "OOC_constraints", yet the Constraints column of the Design runs panel is reporting a constraints set of "bh2_pcie_clean_wrap" which is the name of the sources set.
The Synthesis Run Properties Window - also shown also miss-reports this.
Is my observation correct? If so has this feature been fixed in Vivado 2017.1
05-19-2017 06:35 AM
I don't think this is an issue. This is more a different way to synthesis in out-of-context mode.
The target constaint folder in Vivado is more for the general synthesis than for the OOC.
You may want to try to follow the "Setting a Bottom-Up Out-of-Context Flow" from the UG901 p23.
05-19-2017 07:06 AM
Thanks for your reply. In fact I am following the documentation pages 23-25 of UG901, as I wish to put in place a bottom-up OO flow.
My point is that the user interface is not identifying the correct set of constraints for the OOC synthesis. I have only one set of constraints that I apply to my OOC synth module, if there were several constraints sets how would I know which one I had used? Furthermore if the output from the OOC synthesis is in the .dcp format, then I am unable to verify later which constraint set I had used.