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Visitor alastor100
Visitor
155 Views
Registered: ‎03-16-2017

PUF as AXI4 Peripheral Lite Slave and Selftest error

Hello everybody.

I'll go straight to the point.

I managed to write a ring oscillator puf in vhdl and i successfully tested it using vivado simulator. Basically it can be seen as box which takes a 128 bit input and gives back a 128 bit wide output.

Then I tried to package this ring oscillator puf as an AXI4 IP peripheral, slave interface, lite mode, editing the file like this:

1.PNG2.JPG3.JPG

everything works, I connected it to the zynq7 processing system and I managed to generate the bitstream, export it and launch the SDK.

If I create an helloworld application project and run the reg selftest it fails beacuse it cannot read the register slv_reg1.

4.JPG5.JPG   

I am stuck and I don't know how to proceed further.

I tried to do the same thing with a simple 8 bit adder and it worked fine. What am i doing wrong? 

I have attached the .vhd files of the puf, maybe the problem is there (input and output are 128 bit wide there)

I hope somebody can help me sort this out.

Thanks in advance.

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3 Replies
Scholar dgisselq
Scholar
107 Views
Registered: ‎05-21-2015

Re: PUF as AXI4 Peripheral Lite Slave and Selftest error

I noticed a couple of things.

First, I don't think the following lin is synthesizable:

ro_output <= not(not(ro_input nand feedback)) after 1ns;

It may work in simulation, but I wouldn't expect it to work on actual hardware.

Second, looking over your "counter", I see multiple problems.  I'm not sure of any FPGA that can properly synthesize the following code:

counter: process(counter_input)
variable count : natural := 0;
begin
    if (rising_edge(counter_input)) then
        count <= count + 1;
    end if;

    if count = 10 then
        counter_output <= count;
        count := 0;
    end if;
end process counter;

Have you considered what hardware elements would be required to create this logic?  You have LUTs and FFs available to you.  This logic is not synchronous, nor is it strictly asynchronous.  Perhaps a latch should be inferred?  Indeed, I have no idea how this should be interpreted.

I understand that you are trying to create a ring oscillator.  FPGA logic isn't typically designed to support such a purpose.  Are you sure you need a ring oscillator built within an FPGA?  Are you sure it's even possible to build one?  That the tools will support it?  (They typically don't ...)

Dan

Visitor alastor100
Visitor
86 Views
Registered: ‎03-16-2017

Re: PUF as AXI4 Peripheral Lite Slave and Selftest error

Thank You Dan, I appreciate your tips.

By the way have you got any advice on how to fix these line?

 

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Scholar dgisselq
Scholar
81 Views
Registered: ‎05-21-2015

Re: PUF as AXI4 Peripheral Lite Slave and Selftest error

Sorry, no, I do not know how I'd suggest you fix these.

My own work tends to be highly synchronous.  Had this been a synchronous design, I'm sure I might've figured something out.  From what I understand, though, you are creating a "ring oscillator"--an analog creation that isn't really supported by most FPGA tools.

Had you wanted to create a clock of a known rate from an incoming clock, then I could've helped.

Let me recommend, though, my blog to you.  Perhaps you might find some useful articles there that will help you resolve whatever it is you are actually trying to do?  There's also a Verilog tutorial there.  (Yes, I know you've chosen VHDL.)  However, one of the points I make in the intro refers to the difficulty students often have using parts of the language that were made for simulation only, and not for synthesis--such as the mistake you made above.  Other things you might find valuable include this set of rules for beginners, a discussion of clocks for software engineers, or even a list of reasons why simulation and synthesis might not match.

Perhaps some of those might help?

Dan

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