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Package a block diagram with RTL module reference?

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Visitor
Posts: 13
Registered: ‎03-17-2017
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Package a block diagram with RTL module reference?

Is it possible to package a block diagram with RTL module references in it? I ask because I don't see anything to the contrary in the Xilinx documentation, however I tried to do exactly this and received the following error...

 

[IP_Flow 19-4639] Packaging block design '<>' with a module reference '<>' is not supported in this release.


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Visitor
Posts: 13
Registered: ‎03-17-2017

Re: Package a block diagram with RTL module reference?

My question has been sufficiently answered here...

 

 

https://forums.xilinx.com/t5/Design-Tools-Others/Problem-with-simple-IP-Creation-Module-Reference-not-supported/m-p/755940

 

...Unfortunately, the answer was it is NOT currently possible in Vivado 2016.4. Would like to see this capability added though.

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Visitor
Posts: 13
Registered: ‎03-17-2017

Re: Package a block diagram with RTL module reference?

My question has been sufficiently answered here...

 

 

https://forums.xilinx.com/t5/Design-Tools-Others/Problem-with-simple-IP-Creation-Module-Reference-not-supported/m-p/755940

 

...Unfortunately, the answer was it is NOT currently possible in Vivado 2016.4. Would like to see this capability added though.