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Contributor
Contributor
4,407 Views
Registered: ‎03-17-2017

Package a block diagram with RTL module reference?

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Is it possible to package a block diagram with RTL module references in it? I ask because I don't see anything to the contrary in the Xilinx documentation, however I tried to do exactly this and received the following error...

 

[IP_Flow 19-4639] Packaging block design '<>' with a module reference '<>' is not supported in this release.

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Contributor
Contributor
7,722 Views
Registered: ‎03-17-2017

Re: Package a block diagram with RTL module reference?

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My question has been sufficiently answered here...

 

 

https://forums.xilinx.com/t5/Design-Tools-Others/Problem-with-simple-IP-Creation-Module-Reference-not-supported/m-p/755940

 

...Unfortunately, the answer was it is NOT currently possible in Vivado 2016.4. Would like to see this capability added though.

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4 Replies
Contributor
Contributor
7,723 Views
Registered: ‎03-17-2017

Re: Package a block diagram with RTL module reference?

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My question has been sufficiently answered here...

 

 

https://forums.xilinx.com/t5/Design-Tools-Others/Problem-with-simple-IP-Creation-Module-Reference-not-supported/m-p/755940

 

...Unfortunately, the answer was it is NOT currently possible in Vivado 2016.4. Would like to see this capability added though.

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Participant dave74321
Participant
2,320 Views
Registered: ‎09-29-2016

Re: Package a block diagram with RTL module reference?

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It still does not seem possible (Vivado 2017.4.1)

 

Is sorting this on the Xilinx to-do list?!

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Xilinx Employee
Xilinx Employee
2,259 Views
Registered: ‎07-22-2008

Re: Package a block diagram with RTL module reference?

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Yes, this should be available in Vivado 2018.1.  i just ran a test case and my BD packaged fine with an RTL module in a recent internal build.

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Visitor dwjbosman
Visitor
506 Views
Registered: ‎06-17-2018

Re: Package a block diagram with RTL module reference?

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I am trying to package a block design which includes an RTL module in vivado 2018.2. Packaging finishes without errors.

 

Then I create a block design in which I use the packaged IP. Synthesis completes. But during implementation the following error occurs:

 

"[DRC INBB-3] Black Box Instances: Cell 'design_1_i/bram_mux_0/U0/design_1_i/mux_0' of type 'design_1_bram_mux_0_0_design_1_mux_0_0' has undefined contents and is considered a black box. The contents of this cell must be defined for opt_design to complete successfully."

image.png

IP packager file groups:

image.png

 

During synthesis there is already a warning:

image.png

So why isn't mux.vhd found during design synthesi/implementation?

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