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Contributor
Contributor
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Registered: ‎05-07-2018

Packaged IP Instantiation CLK.FREQ_HZ fixed

I have a BD that I have packaged as IP, then import the associated IP repo into another design for instantiation (into a BD).  I have identified the proper IP clock input associations with AXI interfaces.  So w.r.t. the top level ports of my IP, the clock input freq parameter can be edited and the freq for the associated AXI interface is automatically updated.  When I instantiate the IP, the clock input freq parameter is fixed and cannot be edited.  This causes synthesis to fail since not all the targeted designs have the same AXI frequencies.  Is there a way to indicate to the IP Packager that these clock input freq parameters need to stay editable in the target design BDs (after instantiation)?  This seems like there should be a simple solution to this that I am just not seeing.

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