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6,453 Views
Registered: ‎03-27-2014

Packaging constraint files

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Hello,

 

I have a custom IP which contains a constraint file custom_ip_clocks.xdc, in which I have a single constraint.

I used the Xilinx FIFOs to figure the right way to do it, they're actually identical:

 

set axi_clock [get_clocks -of_objects [get_ports s_axi_aclk]]

set_max_delay -from [get_cells signal_detected_reg[*]] \
-to [get_cells state_reg_reg[*]] \
-datapath_only [get_property -min PERIOD [get_clocks $axi_clock]

Once I use this IP in a design, I can see in the synthesis & implementation log files that this constraint is being used.

If I ever use this IP twice in the same design, I can see that the constraint is only applied to one of the two objects, leading to a faulty timing analysis.

 

Which information am I missing so the embedded constraint file is applied to each instantiation of this IP in a global design? like the Xilinx FIFO for instance? I would like to keep the "embedded constraint files" unaware of what is happening at the upper level, just like the FIFO

 

thank you

 

edit:

I went through the related paragraph in ug1119-vivado-creating-packaging-ip-tutorial.pdf in which Xilinx specifies all of their *_clocks.xdc files are packaged with the "LATE" processing order. I modified the processing order of this very constraint file to that value, but it did not change anything. Processing order would fix a problem like --get_clocks returns null, my problem is the constraint is applied to custom_ip_0 but not to custom_ip_1.

 

I also forgot to mention the problem shows up even when custom_ip_0 and custom_ip_1 share identical configurations (I'm talking about GUI based customizations)

G.W.,
NIST - Time Frequency metrology
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1 Solution

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Xilinx Employee
Xilinx Employee
12,057 Views
Registered: ‎09-20-2012

Re: Packaging constraint files

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Hi @guillaumebres

 

Which version of Vivado are you using?

 

This issue was reported in older versions of vivado and this has been fixed in new releases. Please try using Vivado 2016.2 and let me know if it helps.

Thanks,
Deepika.
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4 Replies
Xilinx Employee
Xilinx Employee
12,058 Views
Registered: ‎09-20-2012

Re: Packaging constraint files

Jump to solution

Hi @guillaumebres

 

Which version of Vivado are you using?

 

This issue was reported in older versions of vivado and this has been fixed in new releases. Please try using Vivado 2016.2 and let me know if it helps.

Thanks,
Deepika.
--------------------------------------------------------------------------------------------
Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left)
0 Kudos
6,253 Views
Registered: ‎03-27-2014

Re: Packaging constraint files

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@vemulad,

 

thank you for your time, I was running 2014.1, I am switching to 2015.4 today.

I will let you know if that solved the problem

G.W.,
NIST - Time Frequency metrology
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Xilinx Employee
Xilinx Employee
6,177 Views
Registered: ‎09-20-2012

Re: Packaging constraint files

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Hi @guillaumebres

 

Any progress on this?

Thanks,
Deepika.
--------------------------------------------------------------------------------------------
Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left)
0 Kudos
6,016 Views
Registered: ‎03-27-2014

Re: Packaging constraint files

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@vemulad,

 

Hi, I upgraded to v2015.4 last week,

it took me a couple of days to upgrade all my IPs but the problem was solved right away, thank you

G.W.,
NIST - Time Frequency metrology
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