03-04-2020 11:59 PM - edited 03-05-2020 12:20 AM
I am new to FPGA development and to this community. I hope the post is in the correct forum.
I would like to create and simulate a block design based on a AXI4 stream describing an ADC with a sample width of 12 bit, an operating sampling frequency fs, and a clock frequency of fs/8. This would result in 8 samples per clock cycle. The 8 samples should be accessible in a register with a width of 8 * 12 bits at every clock cycle. Unfortunately, I do not know how to create such a design, where I receive multiple samples per clock cycle because the ADC sampling frequency is higher than the clock frequency.
Are there any keywords for those types of design I could use to find some examples? And are those designs able to be used for FIR filtering and FFT or do I need one sample per clock cycle?
Also, If you need further information, please let me know.
05-22-2020 08:34 AM - edited 05-22-2020 12:26 PM
(Edit to add: I don't know why this post just showed up as new in the forums for me today. Your header indicates you asked this on March 4, but for some reason its only showed up today..)
Key missing datapoint. What is Fs? 20 MHz? 200 MHz? 500 MHz?
"SuperPipelining" (I think I've seen that term at least) in which you're doing DSP with multiple samples per clock can get VERY messy.
If your sample rate is low enough, it's highly recommended that you only operate on one sample per clock within the internal FPGA calculations. This is NOT saying that your interface to the ADC needs to be one sample per clock. The interface can be wider (as your is); but as soon as your data is within the FPGA, you should buffer and try and operate one sample per clock.
So, depending on your technology, 300-500 MHz processing clocks are achievable with today's FPGAs. At 8 samples per clock at input, that limits your Fs (baseband) to be about max 40-65 MHz, in my opinion. Else things get difficult.
05-22-2020 12:23 PM
Start with your ADC interface. You have to be able to get the data into the FPGA before you can do anything else. What is the clock rate of the ADC-FPGA interface. What is the format of the data bus. Does the ADC use a specific interface like JESD204B or is it a simple parallel data interface. How many samples per clock.
Once the ADC-FPGA interface is worked, then you can start looking at the processing pipeline. If you need to process the data as multiple samples on a slower clock, that can be done but as mentioned before, it can get very messy very quickly. Especially if you are processing 8 samples per clock.
I have seen the term "Super Sample Rate" used for processing multiple samples per clock.
05-22-2020 12:36 PM
Usually this is done when the sample rate is higher than any feasible processing clock in the fpga, for example when the sample rate is several giga-samples per second. This is a common scenario and just about the only way to handle it is with a modern FPGA.
The good news is that many of the IP DSP cores in Vivado are designed to handle multiple samples per clock. For example, the FIR Compiler allows you to specify eight samples per clock and it will handle all the difficult poly-phase processing logic to make it work. The AXI-Streaming interface will be designed to receive multiple samples in the input word. One of the tabs in the core generator GUI shows that formatting.
This is a big deal. Processing multiple samples per clock used to be an enormous hassle. Now it is easy.