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Explorer
Explorer
2,295 Views
Registered: ‎07-03-2014

Parameter not propagating in Block Design

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Hi,

 

I know this problem has been widely covered in these forums, but none of the solutions work for me.

 

I using Vivado 2017.4 and my block design fails to generate due to mismatch in AXIS bus' data width: my Direct Memory Access core has S2MM width as auto and set to 32 bits. This AXIS S2MM bus is connected to an input AXIS bus whose data width is 1 byte (8 bits). This parameter should propagate from AXIS input bus into DMA's S2MM data width, but it didn't.

I tried everything I read in several threads: validate the BD, close the BD, clean it, re-generate output products, open it again, try to validate again. I also deleted the connection bus and re-draw it again, deleted the DMA IP and created it from scratch... Nothing worked, I always got the same warning message:

 

[BD 41-237] Bus Interface property TDATA_NUM_BYTES does not match between /axi_dma_1/S_AXIS_S2MM(4) and /L1_BICM_Data(1)

 

Although this is just a warning, I get a synthesis error due to port mismatch between my top leven ald L1_BICM_Data port.

 

Any solution to this?

 

Thank you in advance.

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Xilinx Employee
Xilinx Employee
2,715 Views
Registered: ‎07-22-2008

Re: Parameter not propagating in Block Design

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The AXI_DMA developer found the problem and fixed has fixed the problem for Vivado 2018.2 (Too late now for 2018.1).

The change that is needed is in the propagate proc in C:\Xilinx\Vivado\2017.4\data\ip\xilinx\axi_dma_v7_1\bd\bd.tcl. 
 

In the bd.tcl, simply change the following line from:

 

if {$tdata_width !=32 && $tdata_width != 64 && $tdata_width != 128 && $tdata_width != 256 && $tdata_width != 512 && $tdata_width != 1024 } {

 

To:

 

if {$tdata_width !=8 && $tdata_width !=16 && $tdata_width !=32 && $tdata_width != 64 && $tdata_width != 128 && $tdata_width != 256 && $tdata_width != 512 && $tdata_width != 1024 } {

 

 

You'll need to close and reopen Vivado. 

If you do not have access to change Files in the install directory, you could use the

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Xilinx Employee
Xilinx Employee
2,256 Views
Registered: ‎07-22-2008

Re: Parameter not propagating in Block Design

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Not sure what you've tried but to ideas are below

1) run "set_property TDATA_NUM_BYTES 1 [get_bd_pins axi_dma_1/S_AXIS_S2MM]"

 

2) Run get_property TDATA_NUM_BYTES.VALUE_SRC [get_bd_pins axi_dma_1/S_AXIS_S2MM]

If the return value is propagated or user, run "set_property TDATA_NUM_BYTES.VALUE_SRC DEFAULT [get_bd_pins axi_dma_1/S_AXIS_S2MM]"

Explorer
Explorer
2,239 Views
Registered: ‎07-03-2014

Re: Parameter not propagating in Block Design

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First of all, thanks for your answer.

 

I tried the following TCL commands:

 

First try:

set_property TDATA_NUM_BYTES 1 [get_bd_intf_pins axi_dma_1/S_AXIS_S2MM]

And I got this message:

WARNING: [BD 41-1642] Cannot set the parameter 'TDATA_NUM_BYTES' on '/axi_dma_1/S_AXIS_S2MM' - Parameter does not exist. 

The parameter actually exists, but Vivado can't find it. See related "Seventh try" for more confusing information about this command.

 

 

Second try:

set_property c_s_axis_s2mm_tdata_width 8 [get_bd_cells axi_dma_1]

And got the message:

WARNING: [BD 41-1642] Cannot set the parameter 'c_s_axis_s2mm_tdata_width' on '/axi_dma_1' - Parameter does not exist. 

The parameter actually exists, but its read-only. That is the parameter set to "auto" on DMA's GUI and it is the parameter whose value is not propagated from BD input pin.

 

 

Third try:

set_property TDATA_NUM_BYTES 1 [get_bd_intf_ports L1_BICM_Data]

And got the message:

 

WARNING: [BD 41-1642] Cannot set the parameter 'TDATA_NUM_BYTES' on '/L1_BICM_Data' - Parameter does not exist. 

I can't figure out what's happening here... Parameter does exist and it is editable, but Vivado cannot set it using TCL commands. However, I can change it in the parameter window after selecting the port.

 

 

 

Forth try:

set_property TDATA_NUM_BYTES 1 [get_bd_pins axi_dma_1/S_AXIS_S2MM]

And got the message:

WARNING: [BD 5-235] No pins matched 'get_bd_pins axi_dma_1/S_AXIS_S2MM'
ERROR: [Common 17-55] 'set_property' expects at least one object.

AXI_DMA_1 core is connected to an BD input bus called "L1_BICM_Data", which is an AXIS interface. So in fact, S_AXIS_S2MM is not a BD input pin, that's why Vivado fails to find the pin. I think it would be more suitable to use third command I listed above.

 

 

Fifth try:

get_property TDATA_NUM_BYTES.VALUE_SRC [get_bd_pins axi_dma_1/S_AXIS_S2MM]

I got the same error message than in forth try for the same reasons. Command I used in seventh try is more suitable.

 

 

Sixth try:

get_property TDATA_NUM_BYTES.VALUE_SRC [get_bd_intf_ports L1_BICM_Data]

And I got "USER" as answer. Can't tell what this means.

 

 

Seventh try:

get_property TDATA_NUM_BYTES.VALUE_SRC [get_bd_intf_pins axi_dma_1/S_AXIS_S2MM]

And I got "DEFAULT" as answer. This blowed my mind... Wasn't it supposed that parameter didn't exist? I used set_parameter in my first try and Vivado replied that parameter didn't exist... I mean, I do know it exists, but I thought Vivado couldn't find it for any reason, so get_parameter should return the same answer.

 

I absolutely confused about this... I always get the same WARNING message when validanting the BD:

 

CRITICAL WARNING: [BD 41-237] Bus Interface property TDATA_NUM_BYTES does not match between /axi_dma_1/S_AXIS_S2MM(4) and /L1_BICM_Data(1)

 

Xilinx Employee
Xilinx Employee
2,190 Views
Registered: ‎07-22-2008

Re: Parameter not propagating in Block Design

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Sorry, It looks like that property is under the CONFIG section.

 

Try

set_property CONFIG.TDATA_NUM_BYTES 1 [get_bd_intf_pins axi_dma_1/S_AXIS_S2MM]

To see the available properties of an interface run

         report_property [get_bd_intf_pins  /axi_dma_1/S_AXIS_S2MM]

 

The other command would be:

        set_property CONFIG.TDATA_NUM_BYTES.VALUE_SRC DEFAULT [get_bd_intf_pins /axi_dma_1/S_AXIS_S2MM]

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Explorer
Explorer
2,178 Views
Registered: ‎07-03-2014

Re: Parameter not propagating in Block Design

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Yes, you're right, I didn't realize I had typed the wrong command.

 

I tried your suggestions, and these were the results:

 

When typed command:

set_property CONFIG.TDATA_NUM_BYTES 1 [get_bd_intf_pins axi_dma_1/S_AXIS_S2MM]

I got the parameter was read-only:

 

CRITICAL WARNING: [BD 41-737] Cannot set the parameter TDATA_NUM_BYTES on /axi_dma_1/S_AXIS_S2MM. It is read-only.

In fact, if that parameter was editable, I could do the same in the "Properties" tab under "External Interface Properties" window.

 

 

When typed the command:

 set_property CONFIG.TDATA_NUM_BYTES.VALUE_SRC DEFAULT [get_bd_intf_pins /axi_dma_1/S_AXIS_S2MM]

I didn't get any error or warning message on the TCL console, but the BD failed to validate again. I got the same warning after validating:

 

CRITICAL WARNING: [BD 41-237] Bus Interface property TDATA_NUM_BYTES does not match between /axi_dma_1/S_AXIS_S2MM(4) and /L1_BICM_Data(1)

It looks like this bug can't be solved by typing TCL commands or changing properties and it's related to something internal to BD engine.

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Explorer
Explorer
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Registered: ‎07-03-2014

Re: Parameter not propagating in Block Design

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Hi,

 

I tried to regenerate the full BD with a TCL command, but it didn't work either. I wasted my time to create the BD from scratch, but parameters still don't propagate.

I can't tell why there are some other BD designs where parameters are propagated correctly and some others not.

Besides, I got a new warning when validating my BD:

 

 [xilinx.com:ip:microblaze:10.0-24] /microblaze_1: There is no D-cache cacheable memory in the address space. Please either turn off the cache or add an IP core with cacheable memory to the design.
 [xilinx.com:ip:microblaze:10.0-24] /microblaze_1: There is no I-cache cacheable memory in the address space. Please either turn off the cache or add an IP core with cacheable memory to the design.
 [BD 41-237] Bus Interface property TDATA_NUM_BYTES does not match between /axi_dma_1/S_AXIS_S2MM(4) and /L1_BICM_Data(1)
 [BD 41-237] Bus Interface property TDATA_NUM_BYTES does not match between /axi_dma_0/S_AXIS_S2MM(4) and /AXI_T2_MI_Reader_0/Data_stream(1)

 

It looks like Microblaze can't reach cached memory range, but actually that's not true. Microblaze's M_AXI_DC and M_AXI_IC interfaces are connected to an AXI interconnect module, whose M0_AXI interface is connected to an external MIG controller throguh and externa interface port (MIG is created in another BD). "Address Editor" reflects the correct DDR range in "External Masters".

Is it safe to ignore this warning?

 

ADDED:

Regarding to those parameters not propagated into DMA core, I got an error when using the SG-DMA driver from my microblaze application. Since DMA core has a 32bit data bus (instead of correct 8bit bus), after setting a BD descriptor to receive 1194 bytes from DMA, I actually receive 1194*4 = 4776. Why? Because SG-DMA driver assumes data bus is 32bit width so 4 bytes are received per DMA beat, instead of actually receiving 1 byte. See the attached screenshot.

 

This became a big headache during this morning, because I allocated a 2048-byte-length buffer to store those 1194 bytes and I was getting unexpected behaviour after DMA completed: some variables where overwritten beyond that 2048-byte buffer boundary because 4776 bytes were actually transferred. Furthermore, I have to read each data byte from receive buffer in a weird way (casting from unsigned int to unsigned char), and forces me to copy the downsized buffer in another buffer to transmit those data in 8-bit AXI-Stream bus.

 

 Isn't there any solution to the propagation parameter problem?

 

SG_DMA_Length.png
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Explorer
Explorer
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Registered: ‎07-03-2014

Re: Parameter not propagating in Block Design

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Two more hints for anybody interested in solving the problem:

 

 1) It looks like parameter TDATA_NUM_BYTES is propagating in the wrong direction: from DMA core to AXI-Stream input port.

I run TCL command:

get_property TDATA_NUM_BYTES.VALUE_SRC [get_bd_intf_ports L1_BICM_Data]

And get "USER"; after checking on Properties window, it is set to 1 byte.

Then I run TCL command:

get_property TDATA_NUM_BYTES.VALUE_SRC [get_bd_intf_pins axi_dma_1/S_AXIS_S2MM]

I get "PROPAGATED", and after generating block, "L1_BICM_Data" port size is 4 bytes, so it is highly likely parameter is propagated in the wrong way.

 

 2) If I create an Xilinx's DMA core outside Block Design (for example, I create an instance in VHDL file), I can freely choose S2MM data width to 8 bits. But then the problem is that XAxiDma driver is not recongnized in SDK, so I can't use the module properly, as I explained here.

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Xilinx Employee
Xilinx Employee
1,935 Views
Registered: ‎07-22-2008

Re: Parameter not propagating in Block Design

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I must have tested with Vivado 2017.3 when I looked at this before.

I was able to reproduce, what I think you are seeing when using Vivado 2017.4.

The propagation is running but just will does not set the TDATA_NUM_WIDTH to less than 4 (Using 4,8, or 16 all worked as you would expect.

I created a short script that shows this Critical Warning with the AXI DMA in 2017.4.  The same script does not have an issue in Vivado 2017.3. 

I have an inquiry into the AXI DMA developer to see if there is a reason behind the change in propagation rules or if it was unintended based on another change. 

          

Explorer
Explorer
1,923 Views
Registered: ‎07-03-2014

Re: Parameter not propagating in Block Design

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@howardp

Thanks for not giving up with this problem. I didn't check with another bus width, I just checked that any time I created a DMA, parameters didn't propagate, no matter what I did: a fresh project, a different ordering in cores, different naming, different FPGA...

 

In fact, I wondered how it comes that nobody else had noticed this problem so far, or how come you weren't able to reproduce it by yourself.

 

Do you think there could be any solution to this for Vivado 2017.4? Our license expired 5 days ago, so even if this is fixed in Vivado 2018.1, we won't be allowed to use that version.

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Xilinx Employee
Xilinx Employee
2,716 Views
Registered: ‎07-22-2008

Re: Parameter not propagating in Block Design

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The AXI_DMA developer found the problem and fixed has fixed the problem for Vivado 2018.2 (Too late now for 2018.1).

The change that is needed is in the propagate proc in C:\Xilinx\Vivado\2017.4\data\ip\xilinx\axi_dma_v7_1\bd\bd.tcl. 
 

In the bd.tcl, simply change the following line from:

 

if {$tdata_width !=32 && $tdata_width != 64 && $tdata_width != 128 && $tdata_width != 256 && $tdata_width != 512 && $tdata_width != 1024 } {

 

To:

 

if {$tdata_width !=8 && $tdata_width !=16 && $tdata_width !=32 && $tdata_width != 64 && $tdata_width != 128 && $tdata_width != 256 && $tdata_width != 512 && $tdata_width != 1024 } {

 

 

You'll need to close and reopen Vivado. 

If you do not have access to change Files in the install directory, you could use the

Explorer
Explorer
936 Views
Registered: ‎07-03-2014

Re: Parameter not propagating in Block Design

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It worked!!

 

Thank you very much, @howardp! I edited the TCL, re-validate the BD and no more warnings appeared. After implementing the project, I checked with SDK that now DMA transfer are indeed 1 byte width.

Your timing was perfect, as I was about to change all my buffer management routines to convert from unsigned int to unsigned char buffers, so you saved me a precious time.

 

Regards!

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