06-10-2020 01:02 PM
I want to pass a filename from upper to lower verilog entity so that the lower entity can use it. I thought of passing the file name through parameter statement and 'include statement as shown below but it does not compile. How do I do this ?
module JESD204_Stimulator # (
parameter string FileName)
`include "FileName" (what is the syntext for this line) ?
06-10-2020 03:21 PM - edited 06-10-2020 03:22 PM
In short, you can't do this.
`include and other pre-processor directives are evaluated very early during the compilation phase of a design.
Parameters are set, and evaluated much later during elaboration. You can't do what you're desiring.
If you can expand a bit more and describe what your higher level goals are perhaps we can help with a different solution.
06-10-2020 05:00 PM
I am using this only in test bench. My Jesd204 simulator sends data to Jesd204 receiver entity that receives data from ADC. My code has 16 different JESD204 entities and I want to send different data to each of them. Since each simulator only connect to one JESD204, I have 16 simulator. If I can pass the file that contains the data to the simulator, I only need to have one simulator code. If I can't pass the file name, I would need to have 16 different simulator codes and the only difference is the 'include "......" statement.
I can do this in VHDL as shown below:
entity JESD204_Stimulator is
generic (FileName : String);
file ControlFile : TEXT is in FileName;
06-10-2020 07:41 PM
What kind of data is in each of the include files? Can you give some examples?
For your VHDL solution, just what do you do with FileName. VHDL doesn't have pre-processor includes as far as I know. Perhaps the solution you used for VHDL would also work for Verilog
06-11-2020 06:49 AM
In VHDL I wrote procedures and functions that use pre-deffine VHDL TEXTIO package commands to parse the file and return the value (hex, integer, string, etc.) if I want to pass "FileName"
my understanding now is 'include in Verilog is the similar to VHDL package "
Is there something like VHDL TEXTIO package in verilog that handle file I/O ?
This is my first project using Verilog.
06-11-2020 08:25 AM
Verilog has a set of I/O tasks and functions as well. ($fopen, $fscanf, etc..). I don't know how much it overlaps with the VHDL TEXTIO packages as I don't know the latter. But those verilog functions should be enough to do what you need.
An alternative is the simple $readmemh/$readmemb files, which just read strings of hexadecimal (or binary) data from a system file into a verilog memory. These are quite simple to use, but limited in function.