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richardhead
Scholar
Scholar
464 Views
Registered: ‎08-01-2012

Possible Defect? Generate_target ignores language settings from .xci file

Im looking at generating IPs from existing .xci files in non-project mode. When I do the following:

set_part xcku040-ffva1156-1-c
read_ip <some_ip>.xci
generate_target all [get_ips *]

it overwrites the VHDL settings in the file with Verilog/Mixed (as these are the vivado defaults) and then writes them back to the file. In non-project mode (and ideally in project mode) if I have an existing XCI I would expect it to respect the settings that already exist in the .XCI:

 <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>        
 <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">VHDL</spirit:configurableElementValue>

To fix, I need to change the project settings (which feels odd, because it's meant to be non-project, though I understand it just creates a project in-memory) before I generate.

set_property TARGET_LANGUAGE  VHDL [current_project]
set_property SIMULATOR_LANGUAGE VHDL [current_project]

For non-project mode - can Vivado be made to respect exsting settings when you're simply reading and IP?

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dsheils
Moderator
Moderator
413 Views
Registered: ‎01-05-2017

Hi @richardhead ,

The behaviour you're seeing is normal. Have a look at the following AR which is still valid:

https://www.xilinx.com/support/answers/63564.html

 

Best Regards,

David

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