Hi all, I'm using Vivado 2018.2 and a K7 device. And there is a problem which confuses me for a long time.
I'm working on a delay line recently and trying to use the output of BUFG 'trig_buffer' to drive 68 cells, which needs a well matched delay with all cells, i.e. almost same delay from 'trig_buffer' to different cells. And the input of BUFG 'trig' is just a output signal of a register, not a clock. But when the systhesis and implementation are done, there is no errors. And I just can't find the BUFG in Schematic or Device which I write in the code definitely. So as a result of no BUFG, the delays from 'trig' to different cells are not well matched. The difference between maximum delay and minimum delay is about 1ns, i.e.68*15ps. But when I delete the 'BUFG' code, the whole project is not working.
So I want to figure out why I can't see the BUFG which is designed by me and how to solve this.