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Registered: ‎02-10-2012

Problem with ISERDESE2 Schematic entry for 7 series FPGA

I was trying to simulate the ISERDESE2 primitive to evaluate the design for my project. I am using Schematic design and when I try to simulate the behavioral model I get the following error :


Type bit_vector of component generic <init_q1> does not match with type of entity generic.


This is in the .vhf file of the schematic. Based on some googling I came across a post where it says I have to change it to "bit" declaration!

I.e    from  INIT_Q1 : bit_vector :=  b"0";


          INIT_Q1 : bit := '0'; 


Now it complies fine after that but the outputs are still red lines.

Before getting into the settings of my ISERDES primitive and further debugging, I want to confirm if the above change is the way to go about it or is there a better fix ? I think editing is auto generated .vhf files is not the way to go about it especially since there is a clear message from Xilinx not to edit such auto generated files!


I am using the latest tools ISE version 14.5 .





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