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Visitor jzmuda
Visitor
4,364 Views
Registered: ‎01-11-2010

Problem with Post Synthesis simulation model (verilog) generated by ISE 10.1 from schematic

Hi!  I am a newbie to Verilog in general and the ISE 10.1 toolset in particular.

 

Hi! I am a newbie to Verilog in general. And to the ISE 10.1 Toolset in particular.

 

But, I do know a few things.  Like how to diagnose a problem.   :-)  

 

Here I use the "replace one component at a time until you find the one that is broken" method.  In particular, here I will replace a Verilog model that ISE generates from my Schematic with "equivalent" hand coded Verilog.  And find that the hand-coded Verilog works, but the Verilog generated by ISE does not.  Hence, my conclusion that there is something wrong with ISE 10.1's translation from Schematic to Verilog. At least in this one case.  

 

(BTW, when I synthesize the design that is captured in the schematic ( in the file "jc2_sch/jc2_top.sch") and load it on an FPGA board, it actually works.  So, it is just the generation of the "Post-synthesis simulation model" that I am suspicious of.  But, that is the part that I NEED.  I really want to be able to simulate design using the ModelSim tool. And, for this, I need the "Post-synthesis simulation model" Verilog that ISE 10.1 produces.) 

 

Or...could it be that I do not know how to compile and load the proper Xilinx libraries that the ModelSim PE Student Edition Simulator needs?  (Since the "auto-generated" Verilog uses a lot of libraries "devices" while the hand code Verilog is much simpler...this is ANOTHER significant difference.  Which could explain the difference in opertion (works versus fails to do anything) that I see between these two Verilog sources when I run them on the ModelSim Simulator.)

 

But I followed all the relevant instructions. 

 

Please see the details, below. 

 

                 *      *      * 

 

Here is the problem that I think I am having with the verilog simulation model that ISE 10.1 generated from my schematic:

 

1. Actually, it is THEIR schematic.  This is from the ICE example. The 4-bit Johnson Counter example. In particular the version of the Johnson Counter project which uses "schematic capture" to capture the design.

 

2. I wanted to use the ModelSim Student Edition (v6.5d) to simulate the project. (I have used Model Sim successfully in the past to simulate other, even simpler projects.)

 

3. Since I wanted to work strictly in Verilog (not VHDL) I modified the original project to generate a Verilog simulation model.  

 

4.  I succeeded in generating the Verilog model.  The resulting file had the name "jc2_top_synthesis.v". It uses all sort of "library" components (like AND, and OR, etc...) 

  

5. I used the Xilinx simluation library compilation wizard to compile all the Xilinx libraries for ModelSim PE. 

 

6.  I then created a ModelSim project.  I included jc2_top_synthesis.v.    I made sure that the Xilinx libraries compiled in step 5 were included in the project. 

 

7.  I added some "verilog test driver code" to "step" the design through a few clock cycles. See the note after this message for the "test driver".  It was simple.  All that I needed to do was toggle the input clock a few times.

 

8. I then ran the resulting code in the simulator. But nothing happens.  The output that I am printing....which should show the "walking bits" pattern of a Johnson Counter...instead shows all 4 bits "stuck" as zeroes.  

 

9. After some thinking, I just replaced the implementation of the jc2_top module that ISE 10.1 had created from the schematic with a "native" Verilog implementation of a 4-bit Johnson Counter.   Exactly equivalent in functionality.   (I obtained it from the same "examples" directory furnished by Xilinx with the ISE toolset.)

 

10.  With this OTHER Verilog code for the jc2_top module...everything works fine.  I run the simulation on ModelSim and I see the "walking ones" pattern I expected.

 

11. So, it would seem that the ISE 10.1 generated Post-Synthesis simulation verilog code is incorrect.

 

12.  Or, could this be a library issue?  Perhaps the implementations of the OR and AND "modules"...that the Verilog code synthesized from the schematic is calling...is incorrect. (The "native" Verilog code for the Johnson Counter is about a 10th the number of lines of the "Compiled Schematic" version.  And doesn't rely upon ANY of the "library modules" like AND or OR.)

 

So, do you have any idea what might be going on here?  I would like to be able to simluate Verilog modules constructed from designs captured in Schematic's...and then generated by ISE.

 

But, right now, I can't.

 

Thanks in advance for your help and insight.

 

Jim

 

Note:  Here is the simple code that I used to "drive" the "functional" simluation.  This "test driver" Verilog code seems to work fine when it is driving the "native" Verilog code for the Johnson Counter.  But, I get no response from the Verilog code generated by the ISE toolset from the Schematic.

 

You would think that the module "jc2_top" should be functionally identical.   No matter HOW it was generated. (Again, the Johnson Counter code that I amusing is from Xilinx own "examples" directory.)

 

 module test_jc2_top;
  reg t_clk;
  reg t_stop;
  reg t_right;
  reg t_left;
  wire [3 : 0] t_q;


  // Instantiate module under test:
  jc2_top u_jc2 (
    .clk(t_clk), .stop(t_stop), .right(t_right), .left(t_left), .q(t_q)
  ); // Using named association


  // Apply stimulus
  // You can see that I am just "twiddling" the clock every 5 time units

  initial
    begin 
      t_clk = 0;
      t_stop = 1;
      t_right = 1;
      t_left = 0;
      #5 t_clk = 1;
      #5 t_clk = 0;
      #5 t_clk = 1;
      #5 t_clk = 0;
      #5 t_clk = 1;
      #5 t_clk = 0;
      #5 t_clk = 1;
      #5 t_clk = 0;
      #5 t_clk = 1;
      #5 t_clk = 0;
      #5 t_clk = 1;
      #5 t_clk = 0;
      #5 t_clk = 1;
      #5 t_clk = 0;
    end

  // Display output:
  initial
    $monitor ( "At time %t,", $time,
               " t_clk = %b, t_stop = %b, t_right = %b, t_left = %b, t_g = %b",
               t_clk, t_stop, t_right, t_left, t_q);
endmodule

 

 


Message Edited by jzmuda on 02-23-2010 01:11 PM
Message Edited by jzmuda on 02-23-2010 01:13 PM
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