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vvj
Explorer
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Registered: ‎09-03-2013

Problem with getting LVDS differential termination on in Vivado 2013.4

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Hi,

 

We have problem getting internal differential termination on for LVDS inputs in Vivado 2013.4 with Zynq7030 chip. This is noticed when measuring some clock signals with oscilloscope.  Clock waveform is not good and there is no difference between if DIFF_TERM is set ON or OFF.

 

I added differential terminations to XDC file.

 

set_property DIFF_TERM TRUE [get_ports PL_CLK_P]

set_property DIFF_TERM TRUE [get_ports PL_CLK_N]

 

I also tried to set DIFF_TERM TRUE to only PL_CLK_P. Same situation, no effect.

 

Setting DIFF_TERM seems to be OK in I/O ports properties  tap after implementation.

 

Like said in : http://xlnx.lithium.com/t5/7-Series-FPGAs/How-do-I-know-if-DIFF-TERM-is-set-to-be-TRUE-correctly-in-Vivado/m-p/456972#M4723

 

Same can be seen with tcl command :

 

get_property DIFF_TERM [get_ports PL_CLK_P]

1

 

I also tried to put terminations directly to IBUFDS generic map -> no effect

 

Do you have any idea why LVDS input signal pair differential termination setting seems not working when tested ??

 

 

Regards,

Ville-Veikko

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vvj
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Registered: ‎09-03-2013

Actually, now clock seems perfectly terminated when measured at the Zynq inputs not from clock source .....Seems also that some routing/load to clock made it look better than without it.

 

Problem is solved.

View solution in original post

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gszakacs
Professor
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Registered: ‎08-14-2007

Make sure you don't have a conflicting value for DIFF_TERM in the IBUFDS instantiation.  The standard template from the Libraries guide sets DIFF_TERM to "false".  And for that matter, I don't really see the need to move the DIFF_TERM attribute into the constraints file, when you have to instantiate the differential input buffer anyway.

-- Gabor
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vvj
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Registered: ‎09-03-2013

OK, I noticed that this DIFF_TERM can be set also to IBUFDS instantiation.

 

I removed constraint from XDC and put it into IBUFDS mapping -> no effect, clock is still not good

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achutha
Xilinx Employee
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Registered: ‎07-01-2010
Moving this post to design entry..
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vvj
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Registered: ‎09-03-2013

 

I tried also to route this PL_CLK differential buffer output to some test output pin. Situation is much better now also in differential input clock measurement !

 

So I guess problem was that there was no use for this clock yet and termination was trimmed away. Now when it is routed to some output termination seems to be implemented ?

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vvj
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Registered: ‎09-03-2013

I noticed that I have used IBUFDS buffer here for clocks also. I think I should use IBUFGDS buffers for clocks. Clocks are by the way in MRCC pins.

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vvj
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Registered: ‎09-03-2013

There is no difference to clock "goodness" whether IBUFDS or IBUFGDS is used.

 

 

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vvj
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Registered: ‎09-03-2013

Actually, now clock seems perfectly terminated when measured at the Zynq inputs not from clock source .....Seems also that some routing/load to clock made it look better than without it.

 

Problem is solved.

View solution in original post

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jmiles1
Contributor
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Registered: ‎05-17-2009

The problem is that the SelectIO wizard doesn't give you the ability to specify DIFF_TERM.  The IBUFDS objects it generates always have DIFF_TERM=FALSE.

 

In general, that particular core generator needs a lot more flexibility.

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w_alkakhi
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Registered: ‎10-15-2019

I am using IBUFGDS buffer with LVDS IOstandards and VCCO= 2.5 V,  and the differential termination is activated (DIFF_TERM => TRUE) ,

It doesn't show any error or warning in the implementation run.

Why it does not show an error?

Respectfully

Wael Alkakhi

 

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