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Observer
Observer
7,751 Views
Registered: ‎08-14-2014

Problem with one clock input pin driving multiple clk_wizard with Vivado block design

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Hi ALL, 

 

I integreted two clock wizard in my block design. However, I want them share same clock input pin and cannot do that.

 

I know the route in HDL: PIN -> IBUFG -> PLLs.

 

But with vivado block design, I cannot create an IBUFG associated with the pin. I've tried to set input of clock wizard as pin, but the IBUFG will be shown in IP resources, means it cannot shared by other IPs.

 

Now the workaround is cascade the two PLLs, but I hope I can connect them paralleled.

 

Any suggestion welcome.

 

Thanks for reading.

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Community Manager
Community Manager
12,766 Views
Registered: ‎07-23-2012
Hi,

You can consider generating the block design with two clocking wizard IPs and connect their CLKIN to two ports.

In the wrapper file, you can connect these two ports to one top-level port.

Regards,
Krishna
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3 Replies
Community Manager
Community Manager
12,767 Views
Registered: ‎07-23-2012
Hi,

You can consider generating the block design with two clocking wizard IPs and connect their CLKIN to two ports.

In the wrapper file, you can connect these two ports to one top-level port.

Regards,
Krishna
-----------------------------------------------------------------------------------------------
Please mark the post as "Accept as solution" if the information provided answers your query/resolves your issue.

Give Kudos to a post which you think is helpful.

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Observer
Observer
7,737 Views
Registered: ‎08-14-2014

Hi Marell,

 

Nice solution! Thank you very much!

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Visitor
Visitor
893 Views
Registered: ‎12-10-2018

This sadly doesn't work anymore because it is not possible to drive multiple buffers with one clkin. If you then disable the buffers of the clock wizards, even more errors arise. Is there a proper solution to use more than one clock wizard? If you use one wizard with multiple outputs, the output clock accuracy drops on both outputs.

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