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cesar182
Adventurer
Adventurer
493 Views
Registered: ‎08-07-2018

Problem with the synthesizer when I update Aurora 64B66B v9.1 to v11.2 in Vivado 2018.3

Greetings ... tell them that I am new using IP cores, and a couple of days ago they passed me a project (vhdl sources and IPs) where the IPs were made in Vivado 2013.4. I have managed to synthesize, simulate and implement this project without any problem in Vivado 2018.3 (no need to update the IPs) ... but now they asked me to update all the IPs of the project and again synthesize, simulate and implement the project. So far I have managed to update a large part of the IPs without affecting the operation of the project. But now I'm having problems updating Aurora 64B66B v9.1 to v11.2, because at the time of synthesizing I get the following errors that are shown in the attached image (synth_error).

I tried to comment the connections do_cc and reset, but I also get another error which is shown in the attached image (synth_error2).

Can someone please help me with this problem, thanks in advance.
I leave attached the Aurora IP that I am using without updating.

Synth_error.PNG
Synth_error2.PNG
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2 Replies
yangc
Xilinx Employee
Xilinx Employee
463 Views
Registered: ‎02-27-2019

Hi @cesar182 ,

I downloaded the IP which you posted , built a new project ,added g1_ipcat_aur.xci ,upgraded IP , generated output products with OOC. There was no any errors in my Messages.  Capture.PNG

So could you take a try following my above steps?

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anusheel
Moderator
Moderator
451 Views
Registered: ‎07-21-2014

@cesar182 

Please compare the tool generated IP Instantiation vs the instantiation used in the RTL to call this IP, I guess the mismatch is expected as the new IP may have some changes. Please cross check and update here. 

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