UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
6,744 Views
Registered: ‎10-03-2014

Problems after checking out from version control system

Jump to solution

Hi,

 

I have a vivado design that I've been using in project mode with Vivado 2013.4 and includes a block design with my own custom IP as well as Xilinx IP. My problem is that certain block design changes cause my project not to work only after I commit and checkout from SVN.

 

For example, I have many UART's which do not have their interrupt lines connected. When I OR these interrupts together and connect them to the Zynq's IRQ_F2P pin, I can get my serial ports to work. However, when I commit these changes to SVN and rebuild the project from a checkout, the project synthesizes/implements without error but the serial ports no longer work. 

 

Here's what I do for committing to SVN:

1) 

# Write block design TCL
write_bd_tcl -force src/bd/system.tcl

# Write project TCL
write_project_tcl -target_proj_dir "./<project_directory>" -no_copy_sources -force project_build.tcl

 

2) I commit these files:

system.tcl

project_build.tcl

system.xdc

and all custom IP .vhd, .v, .xci, .xml,  and .tcl

 

I am guessing my issue stems from Vivado keeping everything in memory rather than constantly saving to files. I think I'm not getting Vivado to save to the file properly and am not committing updated files. Can someone help?

0 Kudos
1 Solution

Accepted Solutions
13,079 Views
Registered: ‎10-03-2014

Re: Problems after checking out from version control system

Jump to solution

Hi again,

 

Thanks for taking a stab at this issue. Turns out, I had an issue that our version control system (SVN) just happen to expose. 

 

Vivado did not update the number of  interrupts connected to the IRQ_F2P pin until after I rebuilt the project (after I’ve commited and checked out the project again from SVN version control system). Consequently, the device tree was setup to use interrupt 89 for UART interrupts rather than 91.

 

More detail:

Before we OR’d together our UART interrupts, we were using interrupt controller cores which did not appear to work properly. We had three of those cores for a total of 3 interrupts to the Zynq on the IRQ_F2P pin. We ditched the interrupt controllers and changed over to OR’ing all the UART interrupts together. When I did this, I now had only 1 interrupt going to the Zynq IRQ_F2P pin. However, Vivado still treated it like there were 3 interrupts so our 1 interrupt was placed at ID# 89 instead of ID# 91 like we expect. The device tree was setup to use interrupt 89 for UART interrupts so this all worked. When I rebuilt the project after checking out from SVN, Vivado updated the IRQ_F2P pin to show that there was only 1 interrupt connected now. So when I re-compiled everything, the UART interrupts were now on interrupt ID# 91. When we updated the device tree to reflect the new interrupt number of 91, everything was working again.

0 Kudos
2 Replies
Scholar drjohnsmith
Scholar
6,724 Views
Registered: ‎07-09-2009

Re: Problems after checking out from version control system

Jump to solution
As a backup, I tend to do an 'archive' first, to a zip file, that seems to force things back to files.

I have asked for an enhancement to Vivado to add a 'committee to file' button, we will see.

Do you have any xdi files to committe also ?

I'd also have a look at the tcl files, to see what files they call up.

I also remember something about TCL files / write_bd_tcl command in the last month on the forum, but I can't immediately find it.
13,080 Views
Registered: ‎10-03-2014

Re: Problems after checking out from version control system

Jump to solution

Hi again,

 

Thanks for taking a stab at this issue. Turns out, I had an issue that our version control system (SVN) just happen to expose. 

 

Vivado did not update the number of  interrupts connected to the IRQ_F2P pin until after I rebuilt the project (after I’ve commited and checked out the project again from SVN version control system). Consequently, the device tree was setup to use interrupt 89 for UART interrupts rather than 91.

 

More detail:

Before we OR’d together our UART interrupts, we were using interrupt controller cores which did not appear to work properly. We had three of those cores for a total of 3 interrupts to the Zynq on the IRQ_F2P pin. We ditched the interrupt controllers and changed over to OR’ing all the UART interrupts together. When I did this, I now had only 1 interrupt going to the Zynq IRQ_F2P pin. However, Vivado still treated it like there were 3 interrupts so our 1 interrupt was placed at ID# 89 instead of ID# 91 like we expect. The device tree was setup to use interrupt 89 for UART interrupts so this all worked. When I rebuilt the project after checking out from SVN, Vivado updated the IRQ_F2P pin to show that there was only 1 interrupt connected now. So when I re-compiled everything, the UART interrupts were now on interrupt ID# 91. When we updated the device tree to reflect the new interrupt number of 91, everything was working again.

0 Kudos