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Participant simonpl
Participant
6,778 Views
Registered: ‎02-11-2015

Problems with design with PCIe Endpoint Block Plus core

Hello,
when I want to synthesize and implement a design with this core, xst is trying to synthesize file for simulation from location <core_name>/simulation/dsport/test_interface.vhd, and crashes after finding 'wait' statement in it. After removing the file process finishes with many warnings of missing file.

 

Second issue is that after reopening ISE and design, core disappears from design view. In file list only .xise file is visible. I can't add xco file, because it "is already in the project", I must remove .xise file an then I can add the source.


I use ISE 14.7 64-bit under Win8.1 and Linux Mint 17.

 

Any ideas how to fix it? I couldn't find any solution on this forum

regards

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2 Replies
Xilinx Employee
Xilinx Employee
6,752 Views
Registered: ‎07-11-2011

Re: Problems with design with PCIe Endpoint Block Plus core

Hi,

 

ISE do not support Windows-8, please use Opearting systems specified in Architecture Support and Requirements chapter of below UG and rerun the flow.

http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_7/irn.pdf

 

Hope this helps

 

-Vanitha

 

 

 

 

 

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Participant simonpl
Participant
6,723 Views
Registered: ‎02-11-2015

Re: Problems with design with PCIe Endpoint Block Plus core

Thanks for reply. I have this problem also under Linux Mint 17.

Does it mean that Xilinx doesn't have any tool that supports devices below 7-series and is compatible with Win8?

 
edit: The same problems are under Win7 64-bit. Any others ideas? It's related to PCIe ipcore, e.g. Aurora8b10b or small cores work fine.
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