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Observer
Observer
2,000 Views
Registered: ‎02-26-2019

Process cannot have both a wait statement and a sensitivity list

Hi all,

I am in VHDL learning stage 

When i am simulating test bench getting Process cannot have both a wait statement and a sensitivity list error

 

--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:39:51 04/20/2019
-- Design Name:
-- Module Name: C:/Users/H335658/Desktop/test_bench/sdfwe/sdfwe_TB1.vhd
-- Project Name: sdfwe
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: sdfwe
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;

ENTITY sdfwe_TB1 IS
END sdfwe_TB1;

ARCHITECTURE behavior OF sdfwe_TB1 IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT sdfwe
PORT(
CLK1 : IN std_logic;
reset : IN std_logic;
CDbar : IN std_logic;
SDbar : IN std_logic;
Q : OUT std_logic;
Qbar : INOUT std_logic;
Q2 : INOUT std_logic;
Q2bar : INOUT std_logic;
Q3 : OUT std_logic;
Q3bar : INOUT std_logic;
BBbusyp : IN std_logic;
PPCLRn : IN std_logic;
clk10uP : IN std_logic;
LASTPTn : IN std_logic;
PTDONEn : IN std_logic;
clk1MHZ_1 : OUT std_logic;
CLK500K_1 : OUT std_logic;
CLK100K_1 : OUT std_logic;
CLK200_1 : OUT std_logic;
TR0p : OUT std_logic_vector(9 downto 0);
CTwrap : OUT std_logic;
q_out_1 : OUT std_logic
);
END COMPONENT;

--Inputs
signal CLK1 : std_logic := '0';
signal reset : std_logic := '1';
signal CDbar : std_logic := '0';
signal SDbar : std_logic := '1';
signal BBbusyp : std_logic := '0';
signal PPCLRn : std_logic := '0';
signal clk10uP : std_logic := '0';
signal LASTPTn : std_logic := '0';
signal PTDONEn : std_logic := '0';
signal flag : std_logic := '0';
signal counter : std_logic := '0';
signal sig_PHAS1An : std_logic := '0';
--BiDirs
signal Qbar : std_logic;
signal Q2 : std_logic;
signal Q2bar : std_logic;
signal Q3bar : std_logic;

--Outputs
signal Q : std_logic;
signal Q3 : std_logic;
signal clk1MHZ_1 : std_logic;
signal CLK500K_1 : std_logic;
signal CLK100K_1 : std_logic;
signal CLK200_1 : std_logic;
signal TR0p : std_logic_vector(9 downto 0);
signal CTwrap : std_logic;
signal q_out_1 : std_logic;

-- Clock period definitions
constant CLK1_period : time := 50 ns;
constant clk10uP_period : time := 20000 ns;
-- constant clk1MHZ_1_period : time := 10 ns;
-- constant CLK500K_1_period : time := 10 ns;
-- constant CLK100K_1_period : time := 10 ns;
-- constant CLK200_1_period : time := 10 ns;

BEGIN

-- Instantiate the Unit Under Test (UUT)
uut: sdfwe PORT MAP (
CLK1 => CLK1,
reset => reset,
CDbar => CDbar,
SDbar => SDbar,
Q => Q,
Qbar => Qbar,
Q2 => Q2,
Q2bar => Q2bar,
Q3 => Q3,
Q3bar => Q3bar,
BBbusyp => BBbusyp,
PPCLRn => PPCLRn,
clk10uP => clk10uP,
LASTPTn => LASTPTn,
PTDONEn => PTDONEn,
clk1MHZ_1 => clk1MHZ_1,
CLK500K_1 => CLK500K_1,
CLK100K_1 => CLK100K_1,
CLK200_1 => CLK200_1,
TR0p => TR0p,
CTwrap => CTwrap,
q_out_1 => q_out_1
);

-- Clock process definitions
CLK1_process :process
begin
CLK1 <= '0';
wait for CLK1_period/2;
CLK1 <= '1';
wait for CLK1_period/2;
end process;
-- ======================================

clk10uP_process :process
begin
clk10uP <= '0';
wait for clk10uP_period/2;
clk10uP <= '1';
wait for clk10uP_period/2;
end process;
-- ======================================


BBBUSYP_process :process(flag,BBbusyp)
begin
if(flag= '0') then
BBbusyp<= '0';
wait for 122 us;
flag <= '1';
else if (flag = '1') then
BBbusyp<= '1';
wait for 22 us;
BBbusyp<= '0';
wait for 166 us;
end if;
end process;



-- ========================================
PTDONEn_process :process
begin
PTDONEn <= '1';
wait for 154.981 us;
PTDONEn <= '0';
wait for 0.019 us;
PTDONEn <= '1';
wait for 198.981 us;
PTDONEn <= '0';
wait for 0.019 us;
end process;
-- ========================================
PPCLRn_process :process
begin
PPCLRn <= '0';
wait for 20 ns;
PPCLRn <= '1';
wait;
end process;

--===========================================

LASTPTn_process :process(counter,LASTPTn)
begin
if(counter<525) then
LASTPTn <= '0';
wait for 0.06 us;
LASTPTn <= '1';
wait for 0.14 us;
counter<= counter+1;
else if(counter = 525) then
counter <= 0;
LASTPTn <= '1';
wait for 16.54 us;
LASTPTn <= '0';
wait for 0.06 us;
LASTPTn <= '1';
wait for 16.54 us;
LASTPTn <= '0';
wait for 0.06 us;
LASTPTn <= '1';
wait for 16.54 us;
end if;
end process;

--===========================================
-- reset_process :process
-- begin
-- reset <= '1';
-- wait for 20 ns;
-- reset <= '0';
-- wait;
-- end process;

-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
CDbar <= '1';
reset <= '0';
wait for CLK1_period*10;

-- insert stimulus here

wait;
end process;
END;

 

Errors.PNG
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9 Replies
Highlighted
Teacher
Teacher
1,992 Views
Registered: ‎10-23-2018

@siva407123_lak 

Per the VHDL spec, you cannot (nor do you need) to have 'wait' and a sensitivity list.

The wait statement cannot be used:

  1. In a process with a sensitivity list
  2. In a procedure called from a process with a sensitivity list.
  3. In a function
  4. In a procedure called from a function

You may want to stimulate these processes with something the simulates a clock

Hope that Helps

If so, Please mark as solution accepted. Kudos also welcomed. :-)

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Highlighted
Teacher
Teacher
1,986 Views
Registered: ‎07-09-2009

what is the intent of this

BBBUSYP_process :process(flag,BBbusyp)
begin
if(flag= '0') then
BBbusyp<= '0';
wait for 122 us;
flag <= '1';
else if (flag = '1') then
BBbusyp<= '1';
wait for 22 us;
BBbusyp<= '0';
wait for 166 us;
end if;
end process;

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
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Highlighted
Observer
Observer
1,959 Views
Registered: ‎02-26-2019

The Intent of this one is generating input pulse with different pulse width.

Attached reference.

please help me if any mistakes in code 

 

 

Regards,

siva

Capture3.PNG
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Highlighted
Teacher
Teacher
1,951 Views
Registered: ‎07-09-2009

your in a test bench, which is behavioural,
do you need this to be synthesis-able ?
<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
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Highlighted
Observer
Observer
1,935 Views
Registered: ‎02-26-2019

Hi,

No,but how to generate clock with different time periods.

Intially i want time periode with 200ns(ton=140 ns and toff=60 ns,number cycles=525) then after ton =16.5 us,toff=60 ns like that it will repeat contineously  continuously

For your information i am attaching snapshot(secon signal)

DISOEwavw (002).bmp
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Highlighted
Teacher
Teacher
1,926 Views
Registered: ‎07-09-2009

do you need this to be synthesis-able ?

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
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Observer
Observer
1,918 Views
Registered: ‎02-26-2019

yes

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Highlighted
Teacher
Teacher
1,898 Views
Registered: ‎07-09-2009

If you need it to be synthesised into a fpga,
how do you understand the delay 166 us to be implemented in the fpga logic?
<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
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Highlighted
Scholar
Scholar
1,893 Views
Registered: ‎08-07-2014

@siva407123_lak,

No,but how to generate clock with different time periods.

Whereever you need, TB or Design, you must have two clock sources and do a MUXing.

If in TB: Simply MUX the two clk signals, as you would MUX two single bit digital signals.

If in Design (to be synth): Use the Xilinx BUFGMUX primitive to switch b/w two clocks. You need to play with Xilinx MMCM/PLL settings to generate the two clocks with your desired duty cycle.

                                           

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