11-24-2009 08:28 AM
with FIFO Generator v4.3 I generated I FIFO with the following properties:
The user guide says on pg. 57 about the programmable full flag:
Note: If a write operation occurs on a rising clock edge that causes the number of words to meet or
exceed the programmable full threshold, then the programmable full flag will assert on the next rising
clock edge. The deassertion of the programmable full flag has a longer delay, and depends on the
relationship between the write and read clocks.
Table 4-18 provides the same information.
In simulation however, the flag is asserted with a latency of five clock cycles. An FPGA programmed with a design using this FIFO verifys the simulated behaviour. Is the doumentation wrong here or am I?
May the latency change through read operations? (I don't mean the deassertion of the programmable full flag here)
Thanks for your answers in advance!