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Registered: ‎03-03-2014

Propagation of ADDR_WIDTH for a custom AXI_LITE IP

Hi All,

I'm using Vivado 2018.3 and this thing is driving me mad !

I want to have my custom IP with a slave AXI_LITE behave like the AXI_BRAM IP does when I change the memory range for the IP in the Address editor, the IP GUI's is automatically updated. My goal is to adjust the address bus size to the memory size inside the IP, the rest of decoding being done by the Interconnect.

So I did a simple Microblaze design.proj_start.png

When I take a look to the IP's before doing anything I have


The araddr for the IC is not defined, and the s_axi_araddr is set to 15 bits corresponding to the defaut configuration of the BRAM Ctrl IP.

Ok that's fine.

Now I set a range of 8K for the BRAM Crtl, which should provide an address bus of 13 bits.

In the IPI, I validate the design which updates the configuration of the IPs


So IC goes to 32 bits and bram_ctrl goes to 13 bits.

I don't know why, but the addresses are not both aligned to 13 bits, but the tool does not complain about this.

If now I set the range to 8K, the bram_ctrl goes to 14 bits.

This what I need !


Now I create a basic custom AXI_LITE IP using the "create and package wizzard" with Lite, Slave, 32 bits, 4 registers parameters. And I add it to the design. The configuration before doing anything is the same as before.


The IC's address is not set, my IP's address is set to 4 bits. (value of the IP's generic parameter C_S00_AXI_ADDR_WIDTH)

If I set a range of 4k for this IP when I validate the design I get


So IC address is as before updated to 32 bits, but the address for the custom IP does not change.


Can anyone guide me to point out what I need to do to get the same behavior as the bram controller  ?



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