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Contributor
Contributor
621 Views
Registered: ‎03-20-2018

Protoinst file keeps getting added to File Groups during IP packaging

Every time I package my design, I keep getting a .protoinst file added to the simulation groups, which throws a warning:

[IP_Flow 19-4308] Project file 'c:/Redlen/ODMB_vfp/ODMB_vfp.srcs/sources_1/bd/vfp_axi_interconnect/sim/vfp_axi_interconnect.protoinst' is not found in the component files. It will be added automatically when merging sources and repackaging. Please remove the file from the source project if this is not desired.

Any idea why this is happening and how to avoid it? I'm not even sure what a protoinst file is, but it shouldn't be required to package the design. 

Currently I am deleting the file before I package everytime, but this is getting time consuming. 

 

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Contributor
Contributor
486 Views
Registered: ‎07-11-2018

I've the same issue.

I found in ug835 that like the protoinst file is for protocol analysys.

Xiliinx: If it will be 'added automatically' later then it should be 'automatically' left out.