UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Visitor cosmin_iorga
Visitor
685 Views
Registered: ‎03-14-2011

Question about Power Integrity IP

Jump to solution

Hello Everyone,

I am trying to make a power integrity IP available to implement in Xilinx FPGAs through Vivado IP core library in a similar way as IBERT for signal integrity is configured.  The power integrity IP will configure the FPGA to be a Vector Network Analyzer with probing ports connected to the on-die power supply domains of the logic core and I/Os. The IP will then measure the power distribution network impedance frequency profile for each power domain port and the coupling between the power domains.  The output will be in the form of PDN impedance and voltage coupling frequency profile graphs and touchstone S-parameter models of the PDN.  I have created "proof-of-concept" designs and I ran a few correlation experiments (more details at http://www.piscanner.com)

 

Does anyone know how to approach this task and/or whom to contact at Xilinx for more information on how to integrate this IP in Vivado tools? 

 

Best Regards,

Cosmin

 

0 Kudos
1 Solution

Accepted Solutions
Moderator
Moderator
637 Views
Registered: ‎02-07-2008

Re: Question about Power Integrity IP

Jump to solution

Hi @cosmin_iorga, you should probably go through the Xilinx Alliance Program for this request.

-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------

View solution in original post

1 Reply
Moderator
Moderator
638 Views
Registered: ‎02-07-2008

Re: Question about Power Integrity IP

Jump to solution

Hi @cosmin_iorga, you should probably go through the Xilinx Alliance Program for this request.

-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------

View solution in original post