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fkhalili
Adventurer
Adventurer
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Registered: ‎11-06-2017

Question about Vivado 2016.3 custom Master AXI Stream Interface generator.

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Hello All, 

I have generated a Master AXI Stream by Vivado 2016.3 IP packager tool. I suppose something is wrong here. If anybody noticed this, please reply this. Here is a snippet of generated VHDL: 

constant NUMBER_OF_OUTPUT_WORDS : integer := 8;

constant depth : integer := NUMBER_OF_OUTPUT_WORDS;

constant bit_num : integer := clogb2(depth);  -- Based on the "clogb2" function, the value of bit_num = 4; 

here is the "clogb2" function:

-- function called clogb2 that returns an integer which has the
-- value of the ceiling of the log base 2.
function clogb2 (bit_depth : integer) return integer is
        variable depth : integer := bit_depth;
        variable count : integer := 1;
        begin
             for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers
                  if (bit_depth <= 2) then
                       count := 1;
                  else
                       if(depth <= 1) then
                              count := count;
                       else
                              depth := depth / 2;
                              count := count + 1;
                       end if;
                 end if;
            end loop;
  return(count);
end;

signal read_pointer : integer range 0 to bit_num-1;  -- In this line the range for "read_pointer" would be from 0 to 3!

 

In the body of code following condition has been applied which I suppose it violates the range of "read_pointer".
 
axis_tlast <= '1' when (read_pointer = NUMBER_OF_OUTPUT_WORDS-1) else '0';


Please correct me if I am wrong. Thanks
fkhm

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1 Solution

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howardp
Xilinx Employee
Xilinx Employee
1,503 Views
Registered: ‎07-22-2008

It appears the range of read_pointer is declared incorrectly.

The value of NUMBER_OF_OUTPUT_WORDS =8.

The range of read_pointer should be 0 to 7 (0 to NUMBER_OF_OUTPUT_WORDS-1).
However, it is written as:
signal read_pointer : integer range 0 to bit_num-1;

Because bit_num = clogb2(NUMBER_OF_OUTPUT_WORDS), this incorrectly makes the range of read_pointer 0 to 3.

If the project language is changed to Verilog and the same steps applied, the Verilog declaration of read_pointer is:  

     reg [bit_num-1:0] read_pointer;

Which correctly allows values from 0 to 7.

 

I've filed a change request to get this fixed for VHDL.

View solution in original post

4 Replies
fkhalili
Adventurer
Adventurer
1,320 Views
Registered: ‎11-06-2017

Hi Again! 

Why nobody reply to this? :( 

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howardp
Xilinx Employee
Xilinx Employee
1,504 Views
Registered: ‎07-22-2008

It appears the range of read_pointer is declared incorrectly.

The value of NUMBER_OF_OUTPUT_WORDS =8.

The range of read_pointer should be 0 to 7 (0 to NUMBER_OF_OUTPUT_WORDS-1).
However, it is written as:
signal read_pointer : integer range 0 to bit_num-1;

Because bit_num = clogb2(NUMBER_OF_OUTPUT_WORDS), this incorrectly makes the range of read_pointer 0 to 3.

If the project language is changed to Verilog and the same steps applied, the Verilog declaration of read_pointer is:  

     reg [bit_num-1:0] read_pointer;

Which correctly allows values from 0 to 7.

 

I've filed a change request to get this fixed for VHDL.

View solution in original post

fkhalili
Adventurer
Adventurer
1,255 Views
Registered: ‎11-06-2017

Hello @howardp

Yes! Exactly, That was what I meant to mention. Thank you for your message :).  Since I am using 2016.3 version, I have no idea if this happens also in latest versions or not. Anyway, I would have liked to report this situation.

Regards,
Farnam

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cahitugur
Observer
Observer
684 Views
Registered: ‎03-31-2014

Same problem with the AXI Slave interface template in Vivado 2018.2,

 

-- bit_num gives the minimum number of bits needed to address 'NUMBER_OF_INPUT_WORDS' size of FIFO.
constant bit_num  : integer := clogb2(NUMBER_OF_INPUT_WORDS-1);

although the range of the bit_num is explained correctly in the comment.

 

The embarrassingthing for Xilinx is this bug still exists after 7 Vivado releases!!!

Incredible!!!

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