I have existing IP (Eg. *.ngc files) such as a (4096x64 Built-In Fifo), which was created with ISE. In ISE, a prog_full_assert
value of "1900", was a valid selection for this FIFO. I am now migrating this design to an UltraScale FPGA.
Since the *.ngc files are not supported in Vivado 2014.3 and later, I have to either re-generate this IP, or use the
convert_ngc command. In Vivado 2016.1, the Vivado IP-Core generator limits prog-full value of a 4096 deep "Built-In-FIFO"
to a range of 2050-4094. In ISE, a value for 1900 was a valid selection. Since I could not re-create this IP with a prog-full
value of 1900, I decided to try the convert_ngc command.
If I use the convert_ngc command on this design, Vivado reports that my *.ngc file was successfully converted to a *.edn file.
In the *.edn file, this parameter is set as below:
When I build the FPGA, will the prog_full output pin of this (4096x64 Built-In-Fifo) be asserted HIGH at a value of 1900?