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Observer asanghi
Observer
141 Views
Registered: ‎01-11-2019

RTL block when instantiated in IPI, has an interface associated with incorrect clock

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I have an RTL design that I want to instantiate and connect with other blocks in IPI. However when I instantiate the design (see the picture attached of the instantiated RTL block), the csr_axi_lite interface automatically gets associated with clk (see picture of the Block interface properties), whereas it should be associated with csr_axi_lite_aclk. I have checked my logic and there is no direct interaction between csr_axi_lite block and clock 'clk'. How does IPI decide which clock an interface to associate with. Is there a way to over-ride the automatic association? Or how to make sure that the interface gets associated with correct clock?

 

 

Screen Shot 2019-04-08 at 11.35.09 AM.png
Screen Shot 2019-04-08 at 11.39.23 AM.png
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Scholar brimdavis
Scholar
103 Views
Registered: ‎04-26-2012

Re: RTL block when instantiated in IPI, has an interface associated with incorrect clock

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@asanghi   "Is there a way to over-ride the automatic association?"

You can add special X_INTERFACE attributes to the ports to control this association, see UG994 v2018.3 pages 212-226

Notes:

If you are using VHDL, the Xilinx IPI attribute parser requires these port attributes to be placed in the architecture, which is illegal VHDL syntax - port attributes are supposed to be placed in the entity per the LRM. (i.e. these attributes may cause errors in some versions of third party simulators unless you use the 'relaxed' syntax checking flags)

I have also seen some horrible Vivado bugs if you are editing RTL module reference attributes while the design is open in IPI, see:

   https://forums.xilinx.com/t5/Design-Entry/RTL-module-referencing/m-p/796968/highlight/true#M14562

-Brian

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Scholar brimdavis
Scholar
104 Views
Registered: ‎04-26-2012

Re: RTL block when instantiated in IPI, has an interface associated with incorrect clock

Jump to solution

@asanghi   "Is there a way to over-ride the automatic association?"

You can add special X_INTERFACE attributes to the ports to control this association, see UG994 v2018.3 pages 212-226

Notes:

If you are using VHDL, the Xilinx IPI attribute parser requires these port attributes to be placed in the architecture, which is illegal VHDL syntax - port attributes are supposed to be placed in the entity per the LRM. (i.e. these attributes may cause errors in some versions of third party simulators unless you use the 'relaxed' syntax checking flags)

I have also seen some horrible Vivado bugs if you are editing RTL module reference attributes while the design is open in IPI, see:

   https://forums.xilinx.com/t5/Design-Entry/RTL-module-referencing/m-p/796968/highlight/true#M14562

-Brian

Observer asanghi
Observer
89 Views
Registered: ‎01-11-2019

Re: RTL block when instantiated in IPI, has an interface associated with incorrect clock

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@brimdavis, Thanks for your response. I was able to associate the clocks by using X_INTERFACE_INFO and X_INTERFACE_PARAM. However for one of the interface, the tool was still associating the incorrect clock (inaddtion to the correct one) with it. This would cause validiation to complain that multiple clocks were associated with the interface. Renaming the culpirt clock resolved this as well for me.

Thank you for your help.

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