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Voyager
Voyager
5,466 Views
Registered: ‎10-06-2015

RTL view has incorrect net names displayed

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I wasn't sure if this should be in the Synthesis or Design Entry Forums, so I placed it here.

 

I am using 2015.4 and trying to view my vhdl code with the RTL viewer.  I see many signal names that are not correct  in the schematic that Vivado created from my HDL source, but if I click on the net the correct name appears in the window to the left of the schematic.  I tried 2016.1 to see if this was addressed in a newer version of the tool, the same problem is seen.  

 

Here's a screen shot, the red arrow show the error while the green arrow shows the good signal names.  

 

god and bad.png

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Guide
Guide
10,226 Views
Registered: ‎01-23-2009

I suspect this is one of the many "interesting" result you get when you set synthesis "flatten_hierarchy = rebuilt" (which is the default).

 

When flatten_hierarchy is set to full or rebuilt, the synthesis tool flattens all hierarchy - it moves all cells and nets to the top level of hierarchy for the actual synthesis. When set to rebuilt, after synthesis is complete, it attempts to rebuild the hierarchy - putting cells back in their original location in the hierarchy. Be definition, this is not a guaranteed thing, since the purpose of flattening was to perform optimization across hierarchical boundaries - after that optimization is done, you have logic that came from a combination of hierarchies. Presumably as part of this, your bus is getting partially exploded.

 

If you care about this (and I absolutely do), then set flatten_hierarchy to "none". When you do this, the hierarchy of your synthesized design will match your RTL exactly, and I suspect all these "oddities" you are seeing will go away.

 

Avrum

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Xilinx Employee
Xilinx Employee
5,464 Views
Registered: ‎02-14-2014

Hello @steve_av,

 

Can you give it a try with Vivado 2016.2 (latest Vivado version)? If you still observe the issue, is it possible to share the design to reproduce the issue?

Regards,
Ashish
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Voyager
Voyager
5,457 Views
Registered: ‎10-06-2015

I'll download that tonight.  I'll probably ditch 2016.1 since I don't have any designs using that version.  I've stayed with 2015.4 since for the most part it's stable for my use.  This RTL view thing has me spending a lot of time second guessing my code and need to get that out of the productivity equation.  

 

This is another oddity, this is with 2015.4.  I have 38 buses each 17 bit wide.  Why does the RTL view arbitrarly decide to break some of the buses down into bits instead of leaving them intact as a bus?    In this example buses 9 through 28 were left as buses by the tool but all the other buses are broken out to bits.  Viewing the rtl is a nightmare... a sea of green!

bus is busted.png

 

 

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Guide
Guide
10,227 Views
Registered: ‎01-23-2009

I suspect this is one of the many "interesting" result you get when you set synthesis "flatten_hierarchy = rebuilt" (which is the default).

 

When flatten_hierarchy is set to full or rebuilt, the synthesis tool flattens all hierarchy - it moves all cells and nets to the top level of hierarchy for the actual synthesis. When set to rebuilt, after synthesis is complete, it attempts to rebuild the hierarchy - putting cells back in their original location in the hierarchy. Be definition, this is not a guaranteed thing, since the purpose of flattening was to perform optimization across hierarchical boundaries - after that optimization is done, you have logic that came from a combination of hierarchies. Presumably as part of this, your bus is getting partially exploded.

 

If you care about this (and I absolutely do), then set flatten_hierarchy to "none". When you do this, the hierarchy of your synthesized design will match your RTL exactly, and I suspect all these "oddities" you are seeing will go away.

 

Avrum

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Voyager
Voyager
5,444 Views
Registered: ‎10-06-2015

NIce.. no secret decoder ring needed now.  Thanks for the tip.  All my signals as are I named them and buses aren't 'busted'.

 

thanks

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