03-27-2018 09:22 AM
Whilst the EDIF stub flow does work (thanks again) , I could not get the post synthesis flow to work.
I could not link the "top level" wrapper file with Verilog netlists.
link_design -name netlist_1
[Project 1-108] Top module 'netlist_wrapper_top.v' not found in any Verilog library
03-28-2018 11:30 PM
I will need to look into the files to understand the issue, most of the time this issue happens because of stub file or incorrect edif generation.
I am moving this post to design entry board for further discussions.
04-04-2018 06:17 AM
Can you please try this in the GUI mode by creating a new post-syntheses design?
You can follow these steps to create a Post-synthesis project using the .v file and open the Synthesized design.
Can you give this a try and see if this will give you a better outcome?
If still failing as before, see if this will produce an additional info/message regarding the issue? If so, please share this with us for examination.
Hope this helps.