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Visitor dbscintera
Visitor
4,909 Views
Registered: ‎05-17-2013

Re: Instantiating block RAMs from within Verilog

I had seen elsewhere in the forums that Vivado generates warnings when using the BRAM macros for memories larger than officially supported but that "it seems to work". I just realized that it really doesn't work. It creates a memory that is aliased repeatedly across the requested memory range.

 

For example, I have a 32768 deep by 32-bits wide true dual-port memory. When I use the BRAM_TDP_MACRO to create it, I get a memory that is 1024 deep by 32-bits wide memory that is aliased 32 times across the address range. This matches up nicely with the comments right in the BRAM_TDP_MACRO header, that a 32-bit data width can be up to 1024 entries deep.

 

What is the right way to do this? These large memories take an eternity in Vivado if they are inferred. For now I'm using create_ip in my build script but we'd like to keep everything within the RTL database if possible.

 

Thanks again,

Dave

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Xilinx Employee
Xilinx Employee
4,906 Views
Registered: ‎09-20-2012

Re: Instantiating block RAMs from within Verilog

Hi Dave,

 

Please create a new thread for different query.

 

I have created a new thread for your post.

 

Cheers,

Deepika.

Thanks,
Deepika.
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