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Observer jfcliche
Observer
6,640 Views
Registered: ‎12-01-2010

Re: Vivado synthesis slower than XST?

Hello all,

 

I've just tried the new Vivado 2013.2 and the Managed IP flow which pre-synthesizes the cores into a checkpoint (.dcp) file.  On a small design, synthesis time was cut by half. I would expect an even bigger gain on a big design that reuse cores many times. This might be the solution I was looking for. I still have synthesis messages like

 

WARNING: [IP_Flow 19-2162] IP 'clock_mmcm' is locked. Locked reason: User override

and

 

Xilinx IP preload is disabled

and I don't know if they have any implication on the synthesis speed but I'm working on it. 

 

Hope this helps,

 

JF

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3 Replies
Xilinx Employee
Xilinx Employee
6,611 Views
Registered: ‎09-20-2012

Re: Vivado synthesis slower than XST?

Hi,

 

one quick check. Compare the utilization (sysntehsis reports) in ISE and Vivado. This can give some clue.

 

Thanks,

Deepika.

Thanks,
Deepika.
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Visitor binupr
Visitor
6,461 Views
Registered: ‎03-15-2010

Re: Vivado synthesis slower than XST?

Can you explain how ti disable "IP Preload" in Vivado 2013.2?

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Visitor binupr
Visitor
6,458 Views
Registered: ‎03-15-2010

Re: Vivado synthesis slower than XST?

I just figured it out :

 

Project Manager--> Project Settings--> IP-> Packager(Tab)-->Automatic Behaviour--> Untick 'Run -upgrade_core when opening IP Packager'

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