06-29-2013 07:54 PM
I've just tried the new Vivado 2013.2 and the Managed IP flow which pre-synthesizes the cores into a checkpoint (.dcp) file. On a small design, synthesis time was cut by half. I would expect an even bigger gain on a big design that reuse cores many times. This might be the solution I was looking for. I still have synthesis messages like
WARNING: [IP_Flow 19-2162] IP 'clock_mmcm' is locked. Locked reason: User override
Xilinx IP preload is disabled
and I don't know if they have any implication on the synthesis speed but I'm working on it.
Hope this helps,
07-01-2013 11:19 PM
one quick check. Compare the utilization (sysntehsis reports) in ISE and Vivado. This can give some clue.
08-16-2013 12:35 AM
I just figured it out :
Project Manager--> Project Settings--> IP-> Packager(Tab)-->Automatic Behaviour--> Untick 'Run -upgrade_core when opening IP Packager'