cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Visitor
Visitor
328 Views
Registered: ‎06-20-2014

Re-generate Verilog module from xci

Jump to solution

I have an xci file for an axi_interconnect IP block from an open source design but not the verilog module to include in RTL compiilation.  How do I generate the module definition so I can use it for synthesis/simulation?

0 Kudos
Reply
1 Solution

Accepted Solutions
Teacher
Teacher
260 Views
Registered: ‎01-28-2008

Hi @petemar 

  When regenerating the output products, you should be getting the stubs and necessary files for synthesis/implementation.

Screenshot 2020-10-22-23_38_17-Generate Output Products_01.png

Screenshot 2020-10-22-23_42_47-Selection_01.png

 The design checkpoint (.dcp) contains the synthesized netlist in .edf form and stub, if needed.

Thanks,

-Pat

 

Give kudos if helpful. Accept as solution if it solves your problem.
https://tuxengineering.com/blog

View solution in original post

6 Replies
Xilinx Employee
Xilinx Employee
320 Views
Registered: ‎01-30-2019

Hi @petemar 
Check the directory in which the output products of the IP are present.

0 Kudos
Reply
Visitor
Visitor
313 Views
Registered: ‎06-20-2014

I inherited this project and the directory is empty.  All I have are the xci files, which are attached.

0 Kudos
Reply
Teacher
Teacher
275 Views
Registered: ‎01-28-2008

Hi @petemar 

  Have you tried adding the .xci files to the project, and then generating the output products for them?

Thanks,

-Pat

 

Give kudos if helpful. Accept as solution if it solves your problem.
https://tuxengineering.com/blog

0 Kudos
Reply
Visitor
Visitor
271 Views
Registered: ‎06-20-2014
I did that and was able to get the instantiation template. However, I need to get the verilog stub and associated ngc/edf to get through synthesis and P&R. How can I get those?
0 Kudos
Reply
Teacher
Teacher
261 Views
Registered: ‎01-28-2008

Hi @petemar 

  When regenerating the output products, you should be getting the stubs and necessary files for synthesis/implementation.

Screenshot 2020-10-22-23_38_17-Generate Output Products_01.png

Screenshot 2020-10-22-23_42_47-Selection_01.png

 The design checkpoint (.dcp) contains the synthesized netlist in .edf form and stub, if needed.

Thanks,

-Pat

 

Give kudos if helpful. Accept as solution if it solves your problem.
https://tuxengineering.com/blog

View solution in original post

Visitor
Visitor
246 Views
Registered: ‎06-20-2014
Got it. Thanks, Pat!
0 Kudos
Reply