Re-generate Verilog module from xci

[petemar]

I have an xci file for an axi_interconnect IP block from an open source design but not the verilog module to include in RTL compiilation.  How do I generate the module definition so I can use it for synthesis/simulation?

[surajc]

Hi @petemar 
Check the directory in which the output products of the IP are present.

[petemar]

I inherited this project and the directory is empty.  All I have are the xci files, which are attached.

[patocarr]

Hi @petemar 

  Have you tried adding the .xci files to the project, and then generating the output products for them?

Thanks,

-Pat

[petemar]

I did that and was able to get the instantiation template. However, I need to get the verilog stub and associated ngc/edf to get through synthesis and P&R. How can I get those?

[patocarr · Accepted solution]

Hi @petemar 

  When regenerating the output products, you should be getting the stubs and necessary files for synthesis/implementation.

 

 The design checkpoint (.dcp) contains the synthesized netlist in .edf form and stub, if needed.

Thanks,

-Pat

[petemar]

Got it. Thanks, Pat!