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houssem1992
Observer
Observer
14,065 Views
Registered: ‎06-28-2015

Re: how do I add a D-FlipFlop to vivado block design?

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Hi,

 

I want to add a D-FlipFlop to the block diagram in vivado but i don't find it  in the IP catalog; Someone help me ?

 

Thanks

 

Houssem

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vuppala
Xilinx Employee
Xilinx Employee
23,077 Views
Registered: ‎04-16-2012

Hi Houssem,

You can achieve it by creating custom IP.
Check this tutorial for creating and packing an IP:http://www.xilinx.com/support/documentation/sw_manuals/xilinx2015_1/ug1119-vivado-creating-packaging-ip-tutorial.pdf

Thanks,
Vinay

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pratham
Scholar
Scholar
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Registered: ‎06-05-2013

@houssem1992 There is no such IP to add a D flip-flop.

-Pratham

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vuppala
Xilinx Employee
Xilinx Employee
23,078 Views
Registered: ‎04-16-2012

Hi Houssem,

You can achieve it by creating custom IP.
Check this tutorial for creating and packing an IP:http://www.xilinx.com/support/documentation/sw_manuals/xilinx2015_1/ug1119-vivado-creating-packaging-ip-tutorial.pdf

Thanks,
Vinay

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athandr
Xilinx Employee
Xilinx Employee
13,820 Views
Registered: ‎07-31-2012

Hi,

 

Why do you need to add the D Flop? In case ths is for latency selection, there are few IP's which have latency control option in the GUI. Please check to see if your IP in the BD has that option for adding latency. If you are looking for a different application altogether, then the above solutions should help.

Thanks,
Anirudh

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sgilbertson
Observer
Observer
11,387 Views
Registered: ‎01-05-2012

So others stumbling on this thread will have a simpler answer than custom IP when all they want to do is latch a handshake signal or something in a block diagram...

 

 

For a D flipflop:

  • Add a "RAM Based Shift Register" IP
  • Check "Clock Enable (CE)" if you need a CE pin
  • Set "Dimensions" to "Manual", width=1 (or however many bits you want to latch), depth=1

You can also do a set/reset flipflop:

  • Add a "Binary Counter" IP
  • Set "Output Width" to 1
  • Check "Restrict Count" and set "Final Count Value (Hex)" to 1
  • In the "Control" tab, check "Clock Enable (CE)" and "Synchronous Clear (SCLR)"
  • Use the "CE" pin for set and the "SCLR" pin for reset

 

lizhang86
Participant
Participant
2,464 Views
Registered: ‎04-25-2017

Hi Sgilbertson,

From the name of the IP I'm assuming the IP will implement the shift register with BRAM.

Do you know if the IP will optimize to use regular distributed FF if my shift register is small enough (eg.3 stages), 

Thanks,

Li

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