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tchin123
Voyager
Voyager
417 Views
Registered: ‎05-14-2017

Re: package IP design fail during OOC synthesis run

I'm using the ZCU102 board with Vivado 2018.2 and my top level design work before packaging. I attached the tcl file in my xgui folder and component.XML file hoping that can shed additional info. My top level design is all VHDL with the following sub module Xilinx IP: FIFO_GENERATOR, BLK_MEM_GEN, AXI_ETHERNET, CLK_WIZ. 

I used the Package your current project option and set my IP location within the project's source directory and choose the include .xci file option. I don't see the PARAM_VALUE.USE_BOARD_FLOW  call in my top_design.tcl script though

 

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ashishd
Xilinx Employee
Xilinx Employee
340 Views
Registered: ‎02-14-2014

Hi @tchin123 ,

Can the entire design be built from scratch using top_design.tcl file? If yes, can you attach that file here?

Regards,
Ashish
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tchin123
Voyager
Voyager
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Registered: ‎05-14-2017

Not familiar with using tcl script but the tcl file was attached above

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ashishd
Xilinx Employee
Xilinx Employee
318 Views
Registered: ‎02-14-2014

Hi @tchin123 ,

That script won't help me to rebuild the design. I am looking for some script which can help me create the design which you're packaging.

Else can you share complete design which you're upgrading?

Regards,
Ashish
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tchin123
Voyager
Voyager
317 Views
Registered: ‎05-14-2017

any idea where within my project directory is it

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ashishd
Xilinx Employee
Xilinx Employee
212 Views
Registered: ‎02-14-2014

Hi @tchin123 ,

In the starting message of this thread, you have mentioned top_design.tcl script. Can you attach this one? I will check if it is sufficient to rebuild the design.

Regards,
Ashish
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tchin123
Voyager
Voyager
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Registered: ‎05-14-2017

Yes, I've attached 2 file  earlier, one of them is the top_design_v1_0 .tcl script.

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