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Visitor intern1
Visitor
189 Views
Registered: ‎01-22-2019

Receiving this error when Validating Block Design : [BD 41-951] Parameter LAYERED_METADATA not found on /clk_wiz_0/clk_out1 .

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Hey All,

So I am receiving this error when validating my block design " [BD 41-951] Parameter LAYERED_METADATA not found on /clk_wiz_0/clk_out1 " . I will attach the portion of my design that is triggering the error. 

Essentially I am using the clocking wizard to create a 10Mhz clock that I want to use to toggle the "Bypass" line of the two adder logic cores. I am making a simple MUX like circuit with available logic. I think it's because the net type out of my clock block is of "type clk" and the input type for the Bypass port is of another type. 

How can I change the type of the Bypass port to clk? Or should I not be using a secondary clock to run my bypass in the first place/ can you offer advice for a better way to toggle my bypass between 0 &1 at constant rate? 

 

Thanks, as always any help is appreciated! 

CLOCKING_error.PNG
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Explorer
Explorer
108 Views
Registered: ‎07-18-2018

Re: Receiving this error when Validating Block Design : [BD 41-951] Parameter LAYERED_METADATA not found on /clk_wiz_0/clk_out1 .

Jump to solution

Try making a custom file that basically does:

 

process(CLK) begin

    If (rising_edge(CLK)) then

        output <= ~output;

    end if;

end process;

And then import it as a module.

Which should more or less make the toggle turn on and off every other clock. Run it twice the speed, and I believe it should then not care that it's a CLK output.

1 Reply
Highlighted
Explorer
Explorer
109 Views
Registered: ‎07-18-2018

Re: Receiving this error when Validating Block Design : [BD 41-951] Parameter LAYERED_METADATA not found on /clk_wiz_0/clk_out1 .

Jump to solution

Try making a custom file that basically does:

 

process(CLK) begin

    If (rising_edge(CLK)) then

        output <= ~output;

    end if;

end process;

And then import it as a module.

Which should more or less make the toggle turn on and off every other clock. Run it twice the speed, and I believe it should then not care that it's a CLK output.