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Referencing RTL Modules for use in Vivado IP Integrator

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Observer
Posts: 30
Registered: ‎07-05-2017
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Referencing RTL Modules for use in Vivado IP Integrator

I was viewing the quick take "Referencing RTL Modules for use in Vivado IP Integrator"  :

https://www.xilinx.com/video/hardware/referencing-rtl-modules-for-vivado-ip-integrator.html

 

I noticed the sample of the RTL verilog files in the quick take tutorial had slave Axi Lite within the verilog RTLdesign. How can I put this simple Axi Lite withing my Verilog so that when I make the RTL into a Module, the AXI is built in. Instead, I am writing my RTL and interfacing with a Slave AXI Lite IP. Just to have an "Slave AXI Lite IP", I have to create and package New IP, and select "SOO_AXI" with Slave Lite option and go in the package and modify the user logic to add the ports to so that I can interface to my Verilog RTL module.

 

I like the way the quick take video describes in how to make a module from a verilog file. This design approach can be simplified if I can get a hold of the "lite_slv_adder_v1_0_s0_axi.v" file, so that I can include the slave axi interface directly in my Verilog RTL.

 

Can someone send me the  sample  file "lite_slv_adder_v1_0_s0_axi.v"?


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Observer
Posts: 30
Registered: ‎07-05-2017

Re: Referencing RTL Modules for use in Vivado IP Integrator

RTL Axi slave 

I figured out how to make my own RTL module with Slave AXI interface within the RTL. I just went to Tools "Create and Package New IP" Created a slave AXI IP, opened it up and copied the RTL code into a verilog file. Now I added my own logic to it and made a RTL module out of the Verilog File. Passed Synthesis/Implementation stage. This way I can write my RTL code and use the "Block Design" method to connect it to the Zynq processor.

 

 

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Observer
Posts: 30
Registered: ‎07-05-2017

Re: Referencing RTL Modules for use in Vivado IP Integrator

RTL Axi slave 

I figured out how to make my own RTL module with Slave AXI interface within the RTL. I just went to Tools "Create and Package New IP" Created a slave AXI IP, opened it up and copied the RTL code into a verilog file. Now I added my own logic to it and made a RTL module out of the Verilog File. Passed Synthesis/Implementation stage. This way I can write my RTL code and use the "Block Design" method to connect it to the Zynq processor.