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bunchyece
Visitor
Visitor
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Registered: ‎02-05-2016

Regarding the input signal segmentation

Hi ,

 

I wanted to ask the ways in which, if I have a signal with 320 samples and I just want to use the last 128 samples, how can I divide the signal so that I am left with only 128 samples in system generator? Do we have any block which helps in doing that?

 

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bwiec
Xilinx Employee
Xilinx Employee
11,411 Views
Registered: ‎08-02-2011

The solution would depend on exactly what you're doing with the data and how it's coming in (i.e. serially vs parallel)? Are you buffering it? Or processing it as it streams in?

 

If buffering it, you put it in a BRAM/FIFO and only assert the write enable for 128 samples, then deassert it for the remaining (320-128)

 

If you're processing it sample-wise, you might just use a clock enable on all your registers to pause everything during those last samples that you don't need. Or a mux to shift in zeros if you need your pipeline to continue processing during those clock cycles.

 

If you provide more details on the problem, we can perhaps provide more specific advice.

www.xilinx.com
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bunchyece
Visitor
Visitor
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Registered: ‎02-05-2016

Hi,

 

I used counter and then a relational block for comparing the sample from where I have to start and then used mux while putting the output of the relational block as enable of the Mux. It worked.

 

Thanks for the reply. :)