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Adventurer
Adventurer
343 Views
Registered: ‎05-18-2018

Repackaging IP for different project and different FPGA

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I am migrating a design from a ZYNQ 7000 to a ZYNQ UltraScale+ in Vivado 2018.3, and one IP block was designed in-house (not by me) for the older 7000 design.

If I follow the IP Packaging wizard, my IP will show in the US+ project, but it does not pass validation. If I just copy the folder from the 7000 project to the US+, same result.

How do I configure a given piece of HDL for a specific FPGA prior to packaging?

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Adventurer
Adventurer
311 Views
Registered: ‎05-18-2018

Re: Repackaging IP for different project and different FPGA

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This worked, so thank you.

I also found that if the IP was not set up for compatibility with the processing system your project is using (7000, UltraScale+, etc.), you can't see the IP in the IP Catalog (since it's not yet compatible), so you can't add it to your block diagram to Edit in IP Packager.

I set up another project in another instance of Vivado using the previous processing system (in my case, a ZYNQ 7000). Because the IP blocks were available in this project, I could edit them in Edit in IP Packager, which allowed me to add US+ to their compatibility lists.

After repackaging them, I went back to my US+ project/instance of Vivado, refreshed my repos in the IP Settings screen, and the IP blocks were now available to me.

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2 Replies
Xilinx Employee
Xilinx Employee
325 Views
Registered: ‎05-22-2018

Re: Repackaging IP for different project and different FPGA

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Hi @joelschad ,


You need to edit the IP(custom IP) and re-customize it for required devices and then add the repo and it will work as per your requirement. 

 

Thanks,

Raj

Adventurer
Adventurer
312 Views
Registered: ‎05-18-2018

Re: Repackaging IP for different project and different FPGA

Jump to solution

 

This worked, so thank you.

I also found that if the IP was not set up for compatibility with the processing system your project is using (7000, UltraScale+, etc.), you can't see the IP in the IP Catalog (since it's not yet compatible), so you can't add it to your block diagram to Edit in IP Packager.

I set up another project in another instance of Vivado using the previous processing system (in my case, a ZYNQ 7000). Because the IP blocks were available in this project, I could edit them in Edit in IP Packager, which allowed me to add US+ to their compatibility lists.

After repackaging them, I went back to my US+ project/instance of Vivado, refreshed my repos in the IP Settings screen, and the IP blocks were now available to me.

0 Kudos