11-23-2020 02:53 AM
Hello,
I have created a block design in Vivado. Trying to add my own IP and Zynq Processing System. But when I run "Run Connection Automation" it gives error.
-Thanks
11-30-2020 04:13 PM
This is a forum post about a similar issue about Zedboard: https://forums.xilinx.com/t5/Processor-System-Design-and-AXI/Arty-S7-DDR-MIG-error/td-p/813066