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Adventurer
Adventurer
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Registered: ‎02-24-2009

Running ISE 14.7, Coregen failes

I'm running ISE 14.7 in Ubuntu on a Virtual Machine.

I can implement a design all the way trough, however I can't generate a Coregen Core (clock wizard).

 

I can fill in the parameters in the clock wizard v3.6, but when generating to core I get:

 

INFO:HDLCompiler:1061 - Parsing VHDL file "/home/kees/Designs/Counter/counter.vhd" into library work

INFO:ProjectMgmt - Parsing design hierarchy completed successfully.

Launching Design Summary/Report Viewer...

The IP Catalog has been reloaded.

INFO:sim:172 - Generating IP...

Resolving generics for 'clkdiv'...

Applying external generics to 'clkdiv'...

Delivering associated files for 'clkdiv'...

WARNING:sim - Component clk_wiz_v3_6 does not have a valid model name for VHDL

   synthesis

Delivering EJava files for 'clkdiv'...

Delivered 3 files into directory

/home/kees/Designs/Counter/ipcore_dir/tmp/_cg/clkdiv

Delivered 1 file into directory

/home/kees/Designs/Counter/ipcore_dir/tmp/_cg/clkdiv

Generating ASY schematic symbol...

Loading device for application Rf_Device from file '6slx9.nph' in environment

/opt/Xilinx/14.7/ISE_DS/ISE/.

ERROR:sim - Tcl error detected initializing IP data model:

   syntax error in expression "1000.000 / 200,000": extra tokens at end of

   expression

       while executing

   "expr  1000.000 / $nsValue"

       (procedure "convert_ns_to_MHz" line 4)

       invoked from within

   "convert_ns_to_MHz $nsValue"

       (procedure "get_speedsfile_ns_data" line 24)

       invoked from within

   "get_speedsfile_ns_data"

       (procedure "clk_wiz_v3_6_utils::get_speedsfile_data" line 40)

       invoked from within

   "clk_wiz_v3_6_utils::get_speedsfile_data"

       (file

   "/opt/Xilinx/14.7/ISE_DS/ISE/coregen/ip/xilinx/primary/com/xilinx/ip/clk_wiz_

   v3_6/gui/clk_wiz_v3_6.tcl" line 1133)

ERROR:sim:938 - Error while preparing for IP customization

ERROR:sim - Failed to initialize IP model.

WARNING:sim:946 - Failed to initialise IP Model for ASY schematic symbol

ERROR:sim:944 - Failed to generate ASY schematic symbol.

ERROR:sim - Failed to generate 'test1'.  Failed to initialise IP Model for ASY

   schematic symbol

 

Wrote CGP file for project 'clkdiv'.

Core Generator create command failed.

 

I can however add the .xco file found in ipcore_dir/tmp/_cg to the ISE project and it will implement.

I've checked the utilization report and I see the added DCM.

 

The mentioned ipcore_dit/tmp/_cg directory has the correct rights.

kees@kees-VirtualBox:~/Designs/Counter/ipcore_dir/tmp/_cg$ ls -l
total 40
drwxrwxr-x 6 kees kees 4096 sept. 26 13:17 clkdiv
-rwxrwxrwx 1 kees kees 2547 sept. 26 13:17 clkdiv.ucf
-rwxrwxrwx 1 kees kees 6335 sept. 26 13:17 clkdiv.vhd
-rwxrwxrwx 1 kees kees 3980 sept. 26 13:17 clkdiv.vho
-rw-rw-r-- 1 kees kees 7949 sept. 26 13:16 clkdiv.xco
-rwxrwxrwx 1 kees kees 2982 sept. 26 13:17 clkdiv.xdc
-rwxrwxrwx 1 kees kees 5119 sept. 26 13:17 clkdiv_xmdf.tcl

 

I know Ubuntu is not on the supported OS list in 2013, but does anybody has any clue how to solve it?

Kees van Egmond
FAE 4 Xilinx @ Avnet Silica Netherlands
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1 Reply
Highlighted
336 Views
Registered: ‎08-02-2017

Change your regional settings to "English (United States)", reboot PC and then try again.

Explanation: 200,000 means 200 for some regional settings, for English regional settings it means 200k

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