Schematic shows I/O port as BI, compile reduces to output only....Need to remain BI
In my design, I have set up a DB0-DB7 port (to uP). To that port I have a Bi-directional buffer (using a subdesign of 8 IOBUFEs...input comes from 8x2 mux, each output goes to an on-chip D-F/F for setting config parameters, the common/Tri-state side goes out to the the DB0-DB7 I/O ports). 2 inputs to the mux are unused and grounded (SEL=1, D2=D3=GND=). The others come from off-chip inputs or on-chip generated signals (6) and 4-bit D latches (2, 4 bits to each side of the mux).
Everything compiles OK, except when I look at the warnings in the CPLD report, the s/w has told me it is converting BI pins DB2-DB5 output ports. Keep in mind I still have the need for inputs also because of my config regs. I've looked at the equations and it's not obvious to me why those 4 specific I/O ports would be changed to output-only. I can almost see why DB2 and DB3 might be changed to Input-only...but even that doesn't make any sense. Here's the actual warning:
[Warning]:Cpld:908 - Converting I/O pin 'DB2' to an output pin. The pin feedback
is unused after optimization. Please verify functionality via simulation.
(I get this for DB2-DB5)
Is there a specific property I can set that will maintain an I/O port as Bi-Di even tho the compilation process thinks it should be otherwise? Am I misreading this report? Have I done something wrong in setting on-chip connections to the databus (DB0-DB7)