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Observer flashman74
Registered: ‎03-26-2009

Schematic top editing!

Hi all,


I'm using schematic for top of my design because is a good total view fo logic.


But it is much frustating to insert net name to connect my components.


In generale a net name is different from pin name, and i must rename every net to 

simulate a comprensive design.


Is there a method to ereditade the pin name on the net ?



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4 Replies
Registered: ‎01-06-2009

Re: Schematic top editing!

I'm not sure I understand you fully. You want the name of the net (schematic wire) to differ from from the port names of a schematic? (Those port names become pin names when the schematic is a top level schematic).


If so, the easiest solution is to insert a buffer between the net and the port. The buffer primitive will be removed by the mapper later in the process automatically. 

Message Edited by kcathcar on 05-05-2009 07:56 AM
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Observer flashman74
Registered: ‎03-26-2009

Re: Schematic top editing!

No, I want the name of the net equal to the net of the port.


For example, I'have two boxes and connect them by some nets. The nets have name as "X..." and I must rename them one to one.


So,is there a method by which a net connected to a port of a box take his name ?

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Newbie hastingsm
Registered: ‎10-20-2009

Re: Schematic top editing!

The problem with doing that automatically is that it is not unusual to connect two (or more) pins with different names with one net.  So the software would not know which name to choose.


An alternative is to change how you do simulations.  Instead of trying to figure out which nets are which on the top level schematic, push down into the block that it is connected to and select the net there.  Although it does depend on the simulation software that you are using, whether that is very easy or not.


Happy Hunting

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Advisor eilert
Registered: ‎08-14-2007

Re: Schematic top editing!

Hi flashman,

hastingsm's tips are very useful, but if you still want to do a global renaming you probably need to write a little program for that purpose.

I assume you are using the Xilinx schematic tool.


The schematic files are plain ASCII and easy to understand.

You have to find the lines wich have  "XLXN" strings in it.

Then you need to identify a pin name (preferably an output, because every net should have just one driver) and copy the name of that pin to the XLXN_?? string. 

Do a global search and replace for this string.


Continue until no  "XLXN" strings remain.


Depending on the intelligence of your program you may have to read in the symbol files too, to identify the outputs.

It's quite simple in perl (the language of choice for such tasks) but can be done in most any language you are familiar with (even VHDL).


If you are really going this way, it would be nice if you post your result here.


Have a nice synthesis




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