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helmutforren
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Registered: ‎06-23-2014

Second base with MIG. 8x data width vs 8x burst

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The MIG interface ends up being 8x64 bits.  The memory burst length is BL8.  Does this mean a single app_wdf_wren strobe that takes in the 8x64 bits from the MIG interface indeed does 8 writes to the memory to be a complete BL8 burst?

 

I'm looking at UG786 page 163 figure 1-75.  It appears to show app_wdf_wren that's one clk wide.   But of course, clk isn't well defined in the diagram.  I'm thinking it's the MIG interface clock, of course, which I've chosen per KC705 recommendations to be the system clock.

 

Do I have this correct?

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vemulad
Xilinx Employee
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Registered: ‎09-20-2012

Hi @helmutforren

 

Thanks.  And if my memory is 64-bits wide, then my app_wdf_data interface will be 512-bits wide.

 

Deepika>> Yes, this is correct.

 

You didn't answer about burst.  But I guess you implied.  To be clear, a single app_wdf_wren will therefore write a whole BL8 burst, right?

 

Deepika>> Yes.

 

Note when I wrote UG786 it was a typo.  I meant UG586.  I had already seen the figure you mention.  It doesn't include any clk speed info, so I wasn't sure.  Those scope figures are also darned hard to read.  I guess the undecipherable writing in the middle is actually ambiguous transition times (X's) and not letters?  Yeah, I don't think figure 1-78 helps any at all beyond figure 1-75.

 

Deepika>> Ya, the figure is not clear. You can send the feedback to the documentation team using "send feedback" button at end of the page.

 

Your point about "ui_clk" is what helps.  Since I was never going to read all 675 pages of UG586, I can now search it for "ui_clk".  I deduce from table 1-17 that it's 1/4 of the DDR3 clock.  Hmmm... doesn't that equal my sys_clk?  For the moment, I want to do some bandwidth calculations.  I realize I'll want to wire to ui_clk.  But I'm wondering now exactly what speed it will run at.  Note per XTP196 advice (xtp196-kc705-mig-c-2014-3.pdf) I selected "Use System Clock" for Reference Clock, if this makes any difference.

 

Deepika>> Yes, the ui_clk is 1/4th of memory clock if you have chosen the PHY to controller clock ratio as 4:1. No the selection of reference clock will not effect this.

 

Bottom line, if on the KC705 my sys_clk is 200MHz and I followed XTP196 advice, then ui_clk will ALSO be 200MHz, right?

 

Deepika>> Yes, The ui_clk frequency will be 200Mhz as memory clock frequency chosen is 800Mhz. 

Thanks,
Deepika.
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vemulad
Xilinx Employee
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Registered: ‎09-20-2012

Hi @helmutforren

 

You have to take ui_clk (MIG output) as reference not sys_clk for driving user interface signals like app_wdf_wren.

 

If your external memory device width is 8 then the user interface bus width (app_wdf_data) will be 64 bits wide.

 

The data put on app_wdf_data bus in one ui_clk cycle will be sent to memory over 4 memory clock cycles. Hope this clarifies.

 

You can refer to figure 1-78 in UG586 for better understanding.

 

Thanks,
Deepika.
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helmutforren
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Registered: ‎06-23-2014

vemulad:

 

Thanks.  And if my memory is 64-bits wide, then my app_wdf_data interface will be 512-bits wide.

 

You didn't answer about burst.  But I guess you implied.  To be clear, a single app_wdf_wren will therefore write a whole BL8 burst, right?

 

Note when I wrote UG786 it was a typo.  I meant UG586.  I had already seen the figure you mention.  It doesn't include any clk speed info, so I wasn't sure.  Those scope figures are also darned hard to read.  I guess the undecipherable writing in the middle is actually ambiguous transition times (X's) and not letters?  Yeah, I don't think figure 1-78 helps any at all beyond figure 1-75.

 

Your point about "ui_clk" is what helps.  Since I was never going to read all 675 pages of UG586, I can now search it for "ui_clk".  I deduce from table 1-17 that it's 1/4 of the DDR3 clock.  Hmmm... doesn't that equal my sys_clk?  For the moment, I want to do some bandwidth calculations.  I realize I'll want to wire to ui_clk.  But I'm wondering now exactly what speed it will run at.  Note per XTP196 advice (xtp196-kc705-mig-c-2014-3.pdf) I selected "Use System Clock" for Reference Clock, if this makes any difference.

 

Bottom line, if on the KC705 my sys_clk is 200MHz and I followed XTP196 advice, then ui_clk will ALSO be 200MHz, right?

 

Thanks again,

Helmut

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vemulad
Xilinx Employee
Xilinx Employee
5,433 Views
Registered: ‎09-20-2012

Hi @helmutforren

 

Thanks.  And if my memory is 64-bits wide, then my app_wdf_data interface will be 512-bits wide.

 

Deepika>> Yes, this is correct.

 

You didn't answer about burst.  But I guess you implied.  To be clear, a single app_wdf_wren will therefore write a whole BL8 burst, right?

 

Deepika>> Yes.

 

Note when I wrote UG786 it was a typo.  I meant UG586.  I had already seen the figure you mention.  It doesn't include any clk speed info, so I wasn't sure.  Those scope figures are also darned hard to read.  I guess the undecipherable writing in the middle is actually ambiguous transition times (X's) and not letters?  Yeah, I don't think figure 1-78 helps any at all beyond figure 1-75.

 

Deepika>> Ya, the figure is not clear. You can send the feedback to the documentation team using "send feedback" button at end of the page.

 

Your point about "ui_clk" is what helps.  Since I was never going to read all 675 pages of UG586, I can now search it for "ui_clk".  I deduce from table 1-17 that it's 1/4 of the DDR3 clock.  Hmmm... doesn't that equal my sys_clk?  For the moment, I want to do some bandwidth calculations.  I realize I'll want to wire to ui_clk.  But I'm wondering now exactly what speed it will run at.  Note per XTP196 advice (xtp196-kc705-mig-c-2014-3.pdf) I selected "Use System Clock" for Reference Clock, if this makes any difference.

 

Deepika>> Yes, the ui_clk is 1/4th of memory clock if you have chosen the PHY to controller clock ratio as 4:1. No the selection of reference clock will not effect this.

 

Bottom line, if on the KC705 my sys_clk is 200MHz and I followed XTP196 advice, then ui_clk will ALSO be 200MHz, right?

 

Deepika>> Yes, The ui_clk frequency will be 200Mhz as memory clock frequency chosen is 800Mhz. 

Thanks,
Deepika.
--------------------------------------------------------------------------------------------
Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left)

View solution in original post

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