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Visitor
Visitor
10,689 Views
Registered: ‎06-15-2015

Setting up clock wizard and simulation fails

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Hi,
here is a simple test project:
my ZedBoard has sys_clk=100Mhz and with the Clocking Wizard I generated a 10Mhz clock.

Then I just created a simulation file:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity clk_wiz_0_testbench is
end clk_wiz_0_testbench;

architecture Behavioral of clk_wiz_0_testbench is

component clk_wiz_0 is
port (    
clk_in1           : in     std_logic;
clk_out1          : out    std_logic;
reset             : in     std_logic;
locked            : out    std_logic);
end component;

signal clk_in1           : std_logic; --global input clock 100Mhz
signal reset           : std_logic;
signal clk_out1        : std_logic;
signal locked          : std_logic;

begin
uut: clk_wiz_0 port map(clk_in1=>clk_in1, clk_out1=>clk_out1, reset=>reset, locked=>locked);

clk_in1_proc: process
begin
    clk_in1 <= '1';
    wait for 5ns;
    clk_in1 <= '0';
    wait for 5ns;
end process;

reset_behav_proc: process
begin
    reset <= '1';
    wait for 200 ns;
    reset <= '0';
    wait;
end process;    
end Behavioral;



All I get is one spike after the reset and then the output clock remains low. See attached image.

What am I doing wrong?


Thank you very much for helping.


Warm regards,
serdarrpf

simulation_clk_wiz_test.PNG
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1 Solution

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Xilinx Employee
Xilinx Employee
19,337 Views
Registered: ‎07-21-2014
Hi,

I can see that "locked" output of PLL/MMCM is not yet high.
run the simulation till this output gets high which indicates that PLL/MMCM is locked to specified output frequency.

Thanks,
Shryeas
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3 Replies
Highlighted
Xilinx Employee
Xilinx Employee
19,338 Views
Registered: ‎07-21-2014
Hi,

I can see that "locked" output of PLL/MMCM is not yet high.
run the simulation till this output gets high which indicates that PLL/MMCM is locked to specified output frequency.

Thanks,
Shryeas
----------------------------------------------------------------------------------------------
Try to search answer for your issue in forums or xilinx user guides before you post a new thread.

Kindly note- Please mark the Answer as "Accept as solution" if information provided solves your query.
Give Kudos (star provided in right) to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------------

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Highlighted
Visitor
Visitor
10,660 Views
Registered: ‎06-15-2015
Ahh thank you. So do you think, it makes sense to wait transmitting my data until "locked" output is high?
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Xilinx Employee
Xilinx Employee
10,646 Views
Registered: ‎07-21-2014
Hi,
Yes, it always makes sense.
Lock output high ensures that the MMCM has achieved phase
alignment within a predefined window and frequency.
LOCKED will be de-asserted if the input clock stops or the phase
alignment is violated.
so it is always a good practice to rely upon this signal and wait till it gets high.

Thanks,
Shreyas
----------------------------------------------------------------------------------------------
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Kindly note- Please mark the Answer as "Accept as solution" if information provided solves your query.
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