Si5324 example project on AC701

[daranda314]

Hi,

Is there a 2019 version of the Si5324 example project? I've downloaded the 2015 version

 https://www.xilinx.com/support/documentation/boards_and_kits/ac701/2015_1/rdf0229-ac701-si5324-c-2015-1.zip

 and follow this

https://www.xilinx.com/member/forms/download/design-license.html?cid=389484&filename=xtp231-ac701-si5324-c-2015-1.pdf

But I have some errors when I run synthesis and I think the reason could be that is written whith an older vivado version

[Synth 8-5809] Error generated from encrypted envelope. ["c:/Users/Diego/Documents/Fiuna/LME/Link test/AC701/ac701_si5324/ac701_si5324.srcs/sources_1/ipshared/xilinx.com/blk_mem_gen_v8_2/834889ee/hdl/blk_mem_gen_v8_2_vhsyn_rfs.vhd":4692]

[patocarr]

Hi @daranda314 

  I took the .zip file linked in your post and opened it with Vivado 2019.2.1, and after upgrading all the IP's, it synthesized without problems. There were some warnings in the IP update process, but didn't cause issues.

  I also ran implementation & bitstream generation which completed as well.

Thanks,

-Pat

[daranda314]

How did you upgrade the IP's?

[patocarr · Accepted solution]

Hi @daranda314 

  The menu option Reports/Report IP Status shows all the IP status and offers to upgrade the selected IPs with a button.

Thanks

-Pat

 

 

[daranda314]

Thank you!