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Visitor
Visitor
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Registered: ‎09-21-2011

Simple VHDL Question - for Novice

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Hi,

 

Just bought a book on VHDL - i used to use ABEL in 1989 to 1991 - but then changed areas of work.

 

My question is - the book i have states the following as an example :

________

type memory_structure is array (0 to 255) of std_logic_vector(7 downto 0)

....

signal memory : memory_structure := (others => (others=>'0'));

----------------

Previous in the text, the book stated that signals will eventually become wires - i assume internal routing.

 

What i do not seem to understand is that if memory_structure is an array 256 deep and integer wide - how will this become a signal - will it just be 32 wires (32bits data width) ?, and each of the elements 0 to 255 can selected individually be passed along the 32 signal paths in sequence if so required  ?

 

Thanks and regards.

 

Richard.

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Teacher
Teacher
8,438 Views
Registered: ‎08-14-2007

Re: Simple VHDL Question - for Novice

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Hi Richard,

all actual Xilinx FPGA Families have some amount of BRAMs.

 

These blocks are quite flexible and can also be used as FIFOs.

You should take a look at the Memory section of the CoreGen tool.

 

It's quite easy to create the desired FIFO IP-Core with it by just entering some parameters.

 

Have a nice synthesis

   Eilert

 

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Teacher
Teacher
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Registered: ‎08-14-2007

Re: Simple VHDL Question - for Novice

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Hi Richard,

basically your textbook is true.

You have declared a set of names, that will be applied to some wires.

 

The question is: Where are these wires, and what is connected to them?

 

In your example you end up with 256*8 wires somewhere.

Now it depends on how you use the declared signal in your code.

 

In the best case you write some code that is recognized as a memory by the synthesis tool , and all the wires are sucked up by a BRAM.

 

In the worst case you are wasting a lot of FFs, or create a big combinatorical mesh with latches.

____

 

Actually in your example the required interface signal needs to be of byte width (7:0), not integer (31:0).

But thats just a detail.

 

The signal "memory" is just used to wire up the memory array.

You need another set of signals like:

signal Address : std_logic_vector(7 downto 0);

signal DataIn : std_logic_vector(7 downto 0);

signal DataOut: std_logic_vector(7 downto 0);

to access the memory.

 

And if everything works well, you will just see these signals in your design, connected to some BRAM block.

 

Take a look at the "Synthesis Constructs" in the ISE Language Templates how to write code that's recognized as a RAM.

 

Have a nice synthesis

  Eilert

 

 

 

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Historian
Historian
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Registered: ‎02-25-2008

Re: Simple VHDL Question - for Novice

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@shadders wrote:

Hi,

 

Just bought a book on VHDL - i used to use ABEL in 1989 to 1991 - but then changed areas of work.

 

My question is - the book i have states the following as an example :

________

type memory_structure is array (0 to 255) of std_logic_vector(7 downto 0)

....

signal memory : memory_structure := (others => (others=>'0'));

----------------

Previous in the text, the book stated that signals will eventually become wires - i assume internal routing.

 

What i do not seem to understand is that if memory_structure is an array 256 deep and integer wide - how will this become a signal - will it just be 32 wires (32bits data width) ?, and each of the elements 0 to 255 can selected individually be passed along the 32 signal paths in sequence if so required  ?

 

Thanks and regards.

 

Richard.


Well, yes, they become wires, in a sense. More to the point, though, it's an array of flip-flops.

Forget the width, for the moment and just consider a one-bit wide memory. To read or write any random bit you provide an address. For read. that address acts as a select for a 256-input multiplexor. For write, that address builds a clock enable for the selected bit. (For writes it probably helps to have a write enable.)

 

If you make this structure 8-bits wide, you simply replicate the above 8 times. If you want it to be 32 bits wide, the structure is replicated 32 times. All of that is somewhat hidden from you; you simply change the width of the range of std_logic_vector(WIDTH-1 downto 0) and it just happens.

----------------------------Yes, I do this for a living.
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Visitor
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Registered: ‎09-21-2011

Re: Simple VHDL Question - for Novice

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Hi Eilert,

 

Thanks - this makes sense now - the BRAM is probably what would need to be implemented not to waste the flip flops - just getting back into this area of work - so will examine the various products that Xilinx provide.

 

My mistake on the integer - i realise now that 8 bits wide was stated in the example.

 

The addressing aspect looks important to remember - my intention is to implement a RAM based FIFO - if BRAM is available in the IC's that Xilinx provide - will make this aspect a lot easier - especially if 24bits or 32bits are easilly implemented. This is for an Audio DAC.

 

Thaks again for your help - much appreciated - i need to read more of the book - only on the first few chapters.

 

Thanks again,

 

Richard.

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Visitor
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Registered: ‎09-21-2011

Re: Simple VHDL Question - for Novice

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Hi Bassman,

 

Thanks - from you reply and Eilert's reply i can see the process of the design. I need to select my target device carfefully to ensure the design is more efficient.

 

Thanks again for your help,

 

Regards,

 

Richard.

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Teacher
Teacher
8,439 Views
Registered: ‎08-14-2007

Re: Simple VHDL Question - for Novice

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Hi Richard,

all actual Xilinx FPGA Families have some amount of BRAMs.

 

These blocks are quite flexible and can also be used as FIFOs.

You should take a look at the Memory section of the CoreGen tool.

 

It's quite easy to create the desired FIFO IP-Core with it by just entering some parameters.

 

Have a nice synthesis

   Eilert

 

View solution in original post

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Visitor
Visitor
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Registered: ‎09-21-2011

Re: Simple VHDL Question - for Novice

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Hi Eilert,

 

Thanks - will be using the smaller CPLD or FPGA with lower pin counts such that BGA packages do not need to be used.

 

Regards,

 

Richard.

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Teacher
Teacher
6,673 Views
Registered: ‎08-14-2007

Re: Simple VHDL Question - for Novice

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Hi Richard,

please be aware that CPLDs do not have BRAMs!

 

Have a nice synthesis

  Eilert

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