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Observer
Observer
301 Views
Registered: ‎10-26-2018

Simple up counter fail to run

Hello all,

Here is a small test counter code in verilog:

 

`timescale 1ns / 1ps

module TestCounter2(
    out_count,
    clk
    );
    
    output [7:0] out_count;
    input  clk;
    
    reg [7:0] out_count;
    
    always @ (posedge clk)
    begin
        out_count <= out_count + 1;
    end
endmodule

I am generating a bitstream for this code to be programmed for a custom zynq 7000 board. I have connected the output to ILA and given a clock input from PS7 FCLK_CLK0 set for 100 Mhz.

 

Below if screen shot of the output seen on hw_ila in vivado

output from hw_ilaoutput from hw_ila

There is no count increment as expected.

Can you please help me to identify the issue.

Thank you in advance.

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2 Replies
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Contributor
Contributor
284 Views
Registered: ‎09-06-2018

Hello,

The clock FCLK_CLK0 is not toggling on the screenshot and is lock to 1. 

Did you check signals FCLK_CLK0 and clk of your module are toggling ?

 

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Observer
Observer
279 Views
Registered: ‎10-26-2018

It looks locked to one because the ILA is sampling at same rate (i.e., 100 MHz) as the clock FCLK_CLK0 and I assume it is only capturing the rising edges of the clock.

Using a simple binary counter IP, i saw that the clock is toggling based on the output from counter which was always incrementing.

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