02-27-2020 05:39 AM
Here is a small test counter code in verilog:
`timescale 1ns / 1ps module TestCounter2( out_count, clk ); output [7:0] out_count; input clk; reg [7:0] out_count; always @ (posedge clk) begin out_count <= out_count + 1; end endmodule
I am generating a bitstream for this code to be programmed for a custom zynq 7000 board. I have connected the output to ILA and given a clock input from PS7 FCLK_CLK0 set for 100 Mhz.
Below if screen shot of the output seen on hw_ila in vivado
There is no count increment as expected.
Can you please help me to identify the issue.
Thank you in advance.
02-27-2020 06:27 AM
It looks locked to one because the ILA is sampling at same rate (i.e., 100 MHz) as the clock FCLK_CLK0 and I assume it is only capturing the rising edges of the clock.
Using a simple binary counter IP, i saw that the clock is toggling based on the output from counter which was always incrementing.