12-17-2018 05:47 PM - edited 12-18-2018 08:55 AM
We have a few IPs - say IP0 and IP1 - that we need to stitch (integrate) together. They include instances of common subIPs like FFTs and memory arrays etc.
When I try to instantiate the IPs i.e. IP0 and IP1 ina top level wrapper, Vivado gives an error for the subIPs - i.e. memory arrays - that different instances of same module with potentially different data are present.
What is the recommended way to do this - preferably without changing the IPs - IP0 and IP1 ?
12-22-2018 10:59 AM
Are all of the IPs fully encapsulated or are they trying to use some shared resource? (e.g. do each instance have their own port mapped instances.. creating separate hardware?) If they are fully encapsulated, I don't see a reason why this would not work.
12-24-2018 08:54 AM - edited 12-24-2018 11:44 AM
@bhawandeepsingh "What is the recommended way to do this - preferably without changing the IPs - IP0 and IP1 ?"
If you're using the IP Integrator flow, put all the shared stuff in it's own directory, then use the "Package a Specified Directory => Package as a library core" option within the IP packager, which makes the shared code visible to other IP as a "library core". You then add these shared IP to IP0 and IP1 as a "sub-core reference" in the Vivado IP Packager.
The following thread has some discussion and manual links on this topic:
If you're doing this in a Verilog RTL flow, you'll need to either give each module a unique name, or use OOC synthesis (which has its' own side effects) :
With a VHDL RTL flow, you can use package or library namespaces to resolve the correct entity.